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CVS commit: [netbsd-10] src/sys/arch/x86/x86



Module Name:    src
Committed By:   martin
Date:           Thu May 15 18:06:57 UTC 2025

Modified Files:
        src/sys/arch/x86/x86 [netbsd-10]: identcpu.c

Log Message:
Pull up following revision(s) (requested by riastradh in ticket #1118):

        sys/arch/x86/x86/identcpu.c: revision 1.135

x86: Reserve space for only the extended CPU state we will use.
CPUID[EAX=0x0d, ECX=0].ECX, i.e., the value of descs[2] after
x86_cpuid2(0x0d, 0, descs), gives the size in bytes of the extended CPU
state for all features supported by the hardware in CPUID[EAX=0x0d,
ECX=0].EAX which can be enabled in XCR0.  However, on i386, it is
senseless to leave TILECFG and TILEDATA enabled, because they are state
for Intel AMX instructions which work only in 64-bit mode.

So, instead of querying the hardware's supported features and maximum
_supported_ extended CPU state size:
1. Query the hardware's supported features.
2. Enable only those supported by software as well (XCR0_FPU).
3. Query the hardware's maximum _enabled_ extended CPU state size.

We will also disable TILECFG and TILEDATA on amd64 for now too
because:
(a) This is not a regression, at least for TILEDATA (and I'm not sure
    any machines ship with TILECFG but not TILEDATA), because the
    size overflowed the PCB page and therefore never worked on amd64
    (PR port-amd64/57661: Crash when booting on Xeon Silver 4416+ in
    KVM/Qemu).
(b) We need a little extra work to properly support reading and
    writing a process's TILECFG and TILEDATA in ptrace(2), and that
    work hasn't been done yet.

While here, write out x86_cpuid2(0x0d, <ecx>, ...) explicitly, rather
than x86_cpuid(0x0d, ...), to make it clear that ECX must be set --
otherwise we may get garbage.  (It is, perhaps, an accident that
x86_cpuid(<eax>, ...) always sets ECX=0, but other CPUID access
paths, like gcc's <cpuid.h> __cpuid(<eax>, ...), do not, so let's
make it clear for the reader.)

XXX When we enable TILECFG and TILEDATA in amd64, we should arrange
to disable them in compat32 processes -- no sense in allocating extra
space for state they can't use anyway, since the Intel AMX
instructions work only in 64-bit mode.  However, selectively
disabling them in some contexts might require hardware support for
XFD, Extended Feature Disable, which is another kettle of fish to
deal with.

PR port-amd64/57661: Crash when booting on Xeon Silver 4416+ in
KVM/Qemu


To generate a diff of this commit:
cvs rdiff -u -r1.123.4.3 -r1.123.4.4 src/sys/arch/x86/x86/identcpu.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




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