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CVS commit: src/sys/arch/riscv/sifive



Module Name:    src
Committed By:   skrll
Date:           Sun Jan 14 07:13:15 UTC 2024

Modified Files:
        src/sys/arch/riscv/sifive: fu540_ccache.c

Log Message:
risc-v: the SiFive FU[57]40 cache controller is present in the JH71x0 SoCs.


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/sifive/fu540_ccache.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




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