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CVS commit: src/sys/kern



Module Name:    src
Committed By:   riastradh
Date:           Sat Jan 16 02:20:00 UTC 2021

Modified Files:
        src/sys/kern: kern_clock.c

Log Message:
entropy: Sample cycle counter or timecounter in hardclock.

Only do so when we're short on entropy, in order to minimize
performance impact.

The sampling should stay close to the time of the actual hardclock
timer interrupt, so that the oscillator driving it determines when we
sample the cycle counter or timecounter, which we hope is driven by
an independent oscillator.

If we used a callout, there might be many other influences -- such as
spin lock delays possibly synchronized with this core's cycle counter
-- that could get between the timer interrupt and the sample.

In the glorious tickless future, this should instead be wired up to
the timer interrupt handler, however that manifests in the future
tickless API.


To generate a diff of this commit:
cvs rdiff -u -r1.143 -r1.144 src/sys/kern/kern_clock.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




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