CVS commit: src/sys/arch/aarch64

["Ryo Shimizu" <ryo%netbsd.org@localhost>]

Module Name:    src
Committed By:   ryo
Date:           Wed Jul  1 08:01:07 UTC 2020

Modified Files:
        src/sys/arch/aarch64/aarch64: aarch64_machdep.c cpu.c trap.c
        src/sys/arch/aarch64/include: armreg.h cpu.h machdep.h

Log Message:
- On some systems with a different cache line size (and DIC,IDC) per CPU, trap "mrs Xt,ctr_el0" instruction
  to return the minimum cache line size of the system to userland.
- add CLIDR_EL1 and CTR_EL0 to struct aarch64_sysctl_cpu_id.

On most systems, cache line size is the same for all CPUs, so this mechanism won't be required.
Rather, this is primarily for errata support, which will be committed later.


To generate a diff of this commit:
cvs rdiff -u -r1.43 -r1.44 src/sys/arch/aarch64/aarch64/aarch64_machdep.c
cvs rdiff -u -r1.51 -r1.52 src/sys/arch/aarch64/aarch64/cpu.c
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/aarch64/aarch64/trap.c
cvs rdiff -u -r1.49 -r1.50 src/sys/arch/aarch64/include/armreg.h
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/aarch64/include/cpu.h
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/aarch64/include/machdep.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.