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CVS commit: src/sys/arch/mips/mips



Module Name:    src
Committed By:   thorpej
Date:           Tue Mar 10 04:04:45 UTC 2020

Modified Files:
        src/sys/arch/mips/mips: trap.c

Log Message:
Comment out the diagnostic message in the TLB_MOD handler that's logged if
pmap_tlb_update_addr() indicates that the VA+ASID was not found in the TLB.
It's a harmless race condition that can happen for legitimate reasons (e.g.
a TLB miss in an interrupt handler that evicts the entry from the TLB).

See discussion:
    http://mail-index.netbsd.org/port-mips/2020/03/07/msg000927.html


To generate a diff of this commit:
cvs rdiff -u -r1.250 -r1.251 src/sys/arch/mips/mips/trap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




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