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CVS commit: src/sys/arch

Module Name:    src
Committed By:   maxv
Date:           Sat Mar 18 13:39:23 UTC 2017

Modified Files:
        src/sys/arch/amd64/amd64: trap.c
        src/sys/arch/i386/i386: trap.c

Log Message:
Mmh, allow iret to be handled when an #SS fault (T_STKFLT) happens. Even
if the sdm is far from being clear, it appears that iret can trigger an #SS
fault if %ss points to a writable but non-present segment; in which case
the kernel would panic, thinking the fault was internal to it.

In particular, userland can create a broken segment in the ldt with
USER_LDT, update its %ss with setcontext and trigger the panic. I don't
think amd64 is affected since USER_LDT does not exist there, and the
changes on tf_ss seem correct - but I'm still adding T_STKFLT for safety.

To generate a diff of this commit:
cvs rdiff -u -r1.93 -r1.94 src/sys/arch/amd64/amd64/trap.c
cvs rdiff -u -r1.286 -r1.287 src/sys/arch/i386/i386/trap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

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