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CVS commit: src/sys/dev/pci
Module Name: src
Committed By: msaitoh
Date: Wed Nov 18 04:24:02 UTC 2015
src/sys/dev/pci: pci_subr.c pcireg.h
- Add the Auto Slot Power Limit Disable bit in Slot Control register and
the Completion Timeout Prefix/Header Log Capable bit in the AER capability
and control register (ECN: Downstream Port Containment (DPC)).
- Add the Poisoned TLP Egress Block bit (ECN: Enhanced DPC).
- Update Link Capabilities 2 register and Link Control 3 register (ECN:
Separate Refclk Independent SSC Architecture (SRIS))
- ECN: Readiness Notifications (RN)
- Add the Retimer Presence Detect Supported bit in the Link Capabilities 2
register and the Retimer Presence Detected bit in the Link Status 2 register
(ECN: Extension Devices)
To generate a diff of this commit:
cvs rdiff -u -r1.145 -r1.146 src/sys/dev/pci/pci_subr.c
cvs rdiff -u -r1.111 -r1.112 src/sys/dev/pci/pcireg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
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