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CVS commit: src/sys/arch/mips/ingenic

Module Name:    src
Committed By:   macallan
Date:           Thu Apr 23 01:20:20 UTC 2015

Modified Files:
        src/sys/arch/mips/ingenic: ingenic_regs.h

Log Message:
more bits & registers

To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/mips/ingenic/ingenic_regs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

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