CVS commit: src/sys/arch/riscv/riscv

["Matt Thomas" <matt%netbsd.org@localhost>]

Module Name:    src
Committed By:   matt
Date:           Tue Mar 31 01:30:50 UTC 2015

Modified Files:
        src/sys/arch/riscv/riscv: locore.S

Log Message:
Since there is only "scratch" system register for use on exception, come
up with a new scheme for its use.  Use PTR_LA, INT_S/INT_L, etc.  Disable
interrupts when returning from exceptions.  Use L_CPU(tp) to get the curcpu
pointer.

When the cpu gets an exception from kernel mode, the sscratch register will be
0 and curlwp will be in the "tp" register.  When the cpu gets an exception from
user mode, the sscratch register will be a pointer to the current lwp.

When an exception happends, the sp is atomically swapped with the sscratch
register.

        If the sp is zero, the exception was a kernel exception and the
        kernel exception path is taken: sp and sscratch are swapped again
        so sscratch is zero again and then a trapframe is allocated from
        the kernel stack.  The t1 register is saved and then the pre-trapframe
        sp is written to the trapframe.

        If sp was non-zero, the exception was from user mode.  The tp register
        is temporarily saved in L_MD_TP(sp) and sp is moved tp.  tp now
        contains a pointer to the current lwp.  A pointer to the user
        trapframe is loaded from L_MD_UTF(tp).  Then t1 is saved in the
        trapframe so it can be used.  The old sp is fetched from sscratch
        while sscratch is zeroed (indicated kernel mode).  The old sp is
        saved in the trapframe.

        Upon exiting the exception, if the exception is returning to user
        mode, the contents of tp is written to sscratch.


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/locore.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.