CVS commit: src/sys/arch/x86/include

["SAITOH Masanobu" <msaitoh%netbsd.org@localhost>]

Module Name:    src
Committed By:   msaitoh
Date:           Thu Jul  3 17:24:33 UTC 2014

Modified Files:
        src/sys/arch/x86/include: cacheinfo.h

Log Message:
Fix some entries:
 - Desc 0x55 and 0xb1 are Instruction TLB but not fixed to 4K.
 - Desc 0x5a and 0xc0 are Data TLB but not fixed to 4K.
 - Desc 0x57 and 0x59 are 4K fixed DTLB.
 - Fix string of desc 0xc2 and it's not fixed to 4K.
 - Desc 0xca is 4K fixed L2 shared TLB.
 - Add desc 0xa0.

BUG: A lot of CPUs have multiple CAI_DTLB and/or CAI_DTLB2 entries. Currently
TLB info is indexed in ci_cinfo[CAI_COUNT], so some info is overwritten.

Nowadays CPUs have very complexed TLBs. It's hard to manage with CAI_* index.
We should think to separate TLB info structure from ci_cinfo[CAI_COUNT]
in struct cpu_info.


To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/x86/include/cacheinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.