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CVS commit: src/sys/arch/i386/isa
Module Name: src
Committed By: dsl
Date: Mon Feb 3 23:00:32 UTC 2014
Since we always run with CR0.NE set (internal fpu using vector 0x10)
npxintr() is only generated when a process executes an FP instruction
and the TS set interrupt takes precedence - so we know the current lwp
owns the fp registers.
It is also then impossible to get a splurious error while saving
Ths lets the npxintr() code be simplified somewhat.
XXX: I'm not at all sure it really DTRT if the process actually wished
to fixup anything in the signal handler (or even if the signal is masked).
To generate a diff of this commit:
cvs rdiff -u -r1.150 -r1.151 src/sys/arch/i386/isa/npx.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
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