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CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips

Module Name:    src
Committed By:   matt
Date:           Fri Dec 23 22:45:27 UTC 2011

Modified Files:
        src/sys/arch/mips/mips [matt-nb5-mips64]: mips_machdep.c

Log Message:
add entries for MIPS 1074K and RMI XLP3XX and XLP8XX.
for mipsNN, use TLB random register in case there are more than 64 TLB entries.
Add cpuname argument to cpu_identify.  Fix bug in mips_page_physaddr.
Print out number of ASIDs in cpu_identify.

To generate a diff of this commit:
cvs rdiff -u -r1. -r1. \

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