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CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name: src
Committed By: matt
Date: Fri Dec 23 22:45:27 UTC 2011
src/sys/arch/mips/mips [matt-nb5-mips64]: mips_machdep.c
add entries for MIPS 1074K and RMI XLP3XX and XLP8XX.
for mipsNN, use TLB random register in case there are more than 64 TLB entries.
Add cpuname argument to cpu_identify. Fix bug in mips_page_physaddr.
Print out number of ASIDs in cpu_identify.
To generate a diff of this commit:
cvs rdiff -u -r18.104.22.168.22.214.171.124 -r126.96.36.199.188.8.131.52 \
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
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