CVS commit: [matt-nb5-mips64] src/sys/arch

["Matt Thomas" <matt%netbsd.org@localhost>]

Module Name:    src
Committed By:   matt
Date:           Sat Dec  3 01:56:56 UTC 2011

Modified Files:
        src/sys/arch/evbmips/rmixl [matt-nb5-mips64]: machdep.c
        src/sys/arch/mips/include [matt-nb5-mips64]: cpu.h pmap.h
        src/sys/arch/mips/mips [matt-nb5-mips64]: cpu_subr.c genassym.cf
            mipsX_subr.S pmap_tlb.c
        src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_subr.S

Log Message:
Rework things a bit for the XLR/XLS/XLP TLB.  Before dealing with the TLB when
MP on the XL?, disable interrupts and take out a lock to prevent concurrent
updates to the TLB.  In the TLB miss and invalid exception handlers, if the
lock is already owned by another CPU, simply return from the exception and
let it continue or restart as appropriate.  This prevents concurrent TLB
exceptions in multiple threads from possibly updating the TLB multiple times
for a single address.


To generate a diff of this commit:
cvs rdiff -u -r1.1.2.36 -r1.1.2.37 src/sys/arch/evbmips/rmixl/machdep.c
cvs rdiff -u -r1.90.16.37 -r1.90.16.38 src/sys/arch/mips/include/cpu.h
cvs rdiff -u -r1.54.26.18 -r1.54.26.19 src/sys/arch/mips/include/pmap.h
cvs rdiff -u -r1.1.2.20 -r1.1.2.21 src/sys/arch/mips/mips/cpu_subr.c
cvs rdiff -u -r1.44.12.29 -r1.44.12.30 src/sys/arch/mips/mips/genassym.cf
cvs rdiff -u -r1.26.36.1.2.49 -r1.26.36.1.2.50 \
    src/sys/arch/mips/mips/mipsX_subr.S
cvs rdiff -u -r1.1.2.18 -r1.1.2.19 src/sys/arch/mips/mips/pmap_tlb.c
cvs rdiff -u -r1.1.2.9 -r1.1.2.10 src/sys/arch/mips/rmi/rmixl_subr.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.