Source-Changes archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

CVS commit: src/sys/arch/x86/x86

Module Name:    src
Committed By:   jym
Date:           Sat Sep 24 10:49:14 UTC 2011

Modified Files:
        src/sys/arch/x86/x86: intel_busclock.c

Log Message:
Be conservative when reading MSR_FSB_FREQ by using rdmsr_safe(). We cannot
tell in advance when new CPU model/family combo will come and trying to
read that MSR early during boot may cause unhandled faults.

To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/x86/x86/intel_busclock.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Home | Main Index | Thread Index | Old Index