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CVS commit: src/sys/arch/mips/mips



Module Name:    src
Committed By:   tsutsui
Date:           Thu Feb 24 16:49:15 UTC 2011

Modified Files:
        src/sys/arch/mips/mips: fp.S

Log Message:
Resurrect silently removed lines in rev 1.37 that update FPU_CSR
in double's inexact or overflow cases.

Now the following tests are passed:
---
tp-start: t_except, 6
tc-start: masked_double
tc-end: masked_double, passed
 :
tc-start: masked_long_double
tc-end: masked_long_double, passed
 :
tp-start: t_subnormal, 2
tc-start: test_double
tc-end: test_double, passed
---

The following ones still fail:
---
tp-start: t_except, 6
 :
tc-start: unmasked_double
tc-se:*** Check failed: /usr/src/tests/lib/libc/ieeefp/t_except.c:269: sicode 
!= t->sicode
tc-end: unmasked_double, failed, 1 checks failed; see output for more details
tc-start: unmasked_float
tc-se:*** Check failed: /usr/src/tests/lib/libc/ieeefp/t_except.c:269: sicode 
!= t->sicode
tc-end: unmasked_float, failed, 1 checks failed; see output for more details
tc-start: unmasked_long_double
tc-se:*** Check failed: /usr/src/tests/lib/libc/ieeefp/t_except.c:269: sicode 
!= t->sicode
tc-end: unmasked_long_double, failed, 1 checks failed; see output for more 
details
tp-end: t_except
 :
tp-start: t_subnormal, 2
 :
tc-start: test_float
tc-end: test_float, failed, Test program received signal 4 (core dumped)
tp-end: t_subnormal
---

- t_except unmasked failures are mentioned in PR port-mips/35327.
- t_subnormal float failure seems trap caused by a FP insn in BDslot
  (I'm not sure if we can use TF_REG_CAUSE in trapframe to see BD bit)


To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39 src/sys/arch/mips/mips/fp.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



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