Source-Changes archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

CVS commit: src/sys/arch/mips/mips

Module Name:    src
Committed By:   tsutsui
Date:           Thu Feb 24 15:52:23 UTC 2011

Modified Files:
        src/sys/arch/mips/mips: locore.S

Log Message:
Fix wrong register usage in mips_fpu_trap():
 - trapframe is the second arg a1, not a3
 - cause is now loaded in a2, not t0 or t3

Fixes kernel panic during tests/lib/libc/ieeefp:
tps-count: 4
tp-start: t_except, 6
tc-start: masked_double
pid 645(t_except): trap: cpu0, TLB modification in kernel mode
status=0x2000ff03, cause=0x4, epc=0x80001420, vaddr=0x4026c8
tf=0xc8b15d00 ksp=0xc8b15da0 ra=0x8024af80 ppl=0x7fff5cd0
kernel: TLB modification trap
Stopped in pid 645.1 (t_except) at      \
        netbsd:mips_fpu_intr+0x74:  sw      t3,144(a3)
though the ieeefp tests still fail in various places.

To generate a diff of this commit:
cvs rdiff -u -r1.179 -r1.180 src/sys/arch/mips/mips/locore.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Home | Main Index | Thread Index | Old Index