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CVS commit: src/sys/arch/sh3
Module Name: src
Committed By: uwe
Date: Fri Feb 4 03:23:33 UTC 2011
__EXCEPTION_ENTRY - "tst" already does logical AND, so shave off extra
"mov" and "and" and just test PSL_MD bit directly.
While here - shuffle around instructions to construct PSL_MD to break
While still here - only interrupt vector uses SSR and SPC as function
args, so don't bother saving them here in r4 and r5. Other vectors
don't need them and interrupt vector can just as well "stc" them
directly before exceptions are enabled.
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/sh3/include/locore.h
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/sh3/sh3/exception_vector.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
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