[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
CVS commit: src/sys/arch/x86/x86
Module Name: src
Committed By: jym
Date: Sun Aug 8 00:48:46 UTC 2010
Some core i7 CPUs report model 0c. In this case, check for the extended
Required to avoid faulting on rdmsr(MSR_FSB_FREQ) early during boot.
Will ask for a pull-up. This affects GENERIC, and most likely, install iso
XXX quick hack. Obtaining FSB through ACPI should be cleaner.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/x86/x86/intel_busclock.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Main Index |
Thread Index |