[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/rmi
Module Name: src
Committed By: cliff
Date: Fri May 28 22:14:53 UTC 2010
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_intr.c rmixl_spl.S
- where possible, stop using CP0 STATUS to disable all interrupts,zero EIMR
instead. more efficient since less meddling with CP0.
assume STATUS[IE] is normally set.
- add rmixl_spl_init_cpu(), to initialize cp0 interrupt control for this cpu
- rmixl_intr_init_cpu() calls rmixl_spl_init_cpu()
to set up CP0 interrupt controls for this cpu
To generate a diff of this commit:
cvs rdiff -u -r18.104.22.168 -r22.214.171.124 src/sys/arch/mips/rmi/rmixl_intr.c
cvs rdiff -u -r126.96.36.199 -r188.8.131.52 src/sys/arch/mips/rmi/rmixl_spl.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Main Index |
Thread Index |