Source-Changes archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

CVS commit: [matt-nb5-mips64] src/sys/arch/mips

Module Name:    src
Committed By:   matt
Date:           Mon Feb 15 07:36:04 UTC 2010

Modified Files:
        src/sys/arch/mips/include [matt-nb5-mips64]: cpu.h locore.h profile.h
        src/sys/arch/mips/mips [matt-nb5-mips64]: lock_stubs.S
            locore.S locore_mips1.S locore_mips3.S mips3_clockintr.c
            mipsX_subr.S mips_machdep.c mips_softint.c spl.S trap.c
Added Files:
        src/sys/arch/mips/include [matt-nb5-mips64]: intr.h

Log Message:
Completely redo how interrupts and SPL are handled in NetBSD/mips.
[XXX locore_mips1.S still needs to adapted.]

Nested interrupts now work.  Except for MIPS_SOFT_MASK and MIPS_SR_INT_IE,
how interrupts work is completely abstracted.  spl is handled through the
mips_splsw table.  Direct manipulation of the status register is no longer
done (except for MIPS_SR_INT_IE).  A new <mips/intr.h> contains the common
IPL/IST/spl* definitions for all ports.

Interrupt delivery is completely different.  Clock interrupts may interrupt
device interrupts.  ci_idepth is now handled by the caller of cpu_intr as
are softints (both can be optimized/simplified in the case of interrupts of
usermode code).  cpu_intr has new arguments and now get called at IPL_HIGH
with MIPS_SR_INT_IE set and its logic is:

cpu_intr(int ppl, vaddr_t pc, uint32_t status)
        int ipl;
        uint32_t pending;
        while (ppl < (ipl = splintr(&pending))) {
                splx(ipl);              /* enable interrupts */
                <handle pending interrupts>
                (void)splhigh();        /* disable interrupts */

mipsX_subr.S has been reworked.  All user handlers (user_intr, systemcall,
user_gen_exception) now use common return to usermode code in lwp_trampoline.
ast() has changed to void ast(void) since the previous pc argument was never

The playstation IPL_ICU_MASK support has been nuked.
MIPS_DYNAMIC_STATUS_MASK may soon be nuked soon.

A bunch of debugging code was left conditionalized by PARANOIA.  If this
code detects a bug, it will enter an infinite loop.  It is expected that
the kernel will be debugged in a simulator or with a hardware debugger so
that the state at that point can be analyzed.

To generate a diff of this commit:
cvs rdiff -u -r1.90.16.18 -r1.90.16.19 src/sys/arch/mips/include/cpu.h
cvs rdiff -u -r0 -r1.3.96.2 src/sys/arch/mips/include/intr.h
cvs rdiff -u -r1. -r1. \
cvs rdiff -u -r1.20 -r1.20.96.1 src/sys/arch/mips/include/profile.h
cvs rdiff -u -r1.44.12.15 -r1.44.12.16 src/sys/arch/mips/mips/
cvs rdiff -u -r1.9.18.6 -r1.9.18.7 src/sys/arch/mips/mips/lock_stubs.S
cvs rdiff -u -r1.167.38.12 -r1.167.38.13 src/sys/arch/mips/mips/locore.S
cvs rdiff -u -r1. -r1. \
cvs rdiff -u -r1.93.38.4 -r1.93.38.5 src/sys/arch/mips/mips/locore_mips3.S
cvs rdiff -u -r1.8 -r1.8.12.1 src/sys/arch/mips/mips/mips3_clockintr.c
cvs rdiff -u -r1. -r1. \
cvs rdiff -u -r1. -r1. \
cvs rdiff -u -r1.1.2.3 -r1.1.2.4 src/sys/arch/mips/mips/mips_softint.c
cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/mips/spl.S
cvs rdiff -u -r1.217.12.18 -r1.217.12.19 src/sys/arch/mips/mips/trap.c
cvs rdiff -u -r1. -r1. \

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Home | Main Index | Thread Index | Old Index