CVS commit: [netbsd-5] src

[Manuel Bouyer <bouyer%netbsd.org@localhost>]

Module Name:    src
Committed By:   bouyer
Date:           Mon May 18 19:43:56 UTC 2009

Modified Files:
        src/sys/arch/x86/include [netbsd-5]: cacheinfo.h
        src/usr.sbin/cpuctl/arch [netbsd-5]: i386.c

Log Message:
Pull up following revision(s) (requested by pgoyette in ticket #761):
        sys/arch/x86/include/cacheinfo.h: revisions 1.11, 1.12
        usr.sbin/cpuctl/arch/i386.c: revisions 1.18, 1.19 via patch
1. Extend CPU probe of Intel processors to handle extended-models.  This
    allows us to properly identify new Intel 45nm processors, Core i7,
    Atom, and the 45nm Xeon MP.
2. Properly decode several new Intel cache descriptors, as listed in the
    most recent (March 2009) edition of Intel's Application Note 485.
Addresses my PR bin/41289
Addresses my PR bin/41290


To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.9.8.1 src/sys/arch/x86/include/cacheinfo.h
cvs rdiff -u -r1.13.2.2 -r1.13.2.3 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.