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CVS commit: src/sys/arch/arm/arm
Module Name: src
Committed By: matt
Date: Wed Oct 15 16:38:10 UTC 2008
Make sure the register used is 0 when doing ops which affect the entire
cache or tlb.
To generate a diff of this commit:
cvs rdiff -r1.1 -r1.2 src/sys/arch/arm/arm/cpufunc_asm_fa526.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
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