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CVS commit: src/sys/arch/x86

Module Name:    src
Committed By:   chris
Date:           Sun May 25 15:19:22 UTC 2008

Modified Files:
        src/sys/arch/x86/include: specialreg.h
        src/sys/arch/x86/x86: errata.c

Log Message:
Add detection of errata for AMD Family 10h steppings A and 2.  Covering
254: Internal Resource Livelock Involving Cached TLB Reload
261: Processor May Stall Entering Stop-Grant Due to Pending Data
     Cache Scrub
298: L2 Eviction May Occur During Processor Operation To Set
     Accessed or Dirty Bit
309: Processor Core May Execute Incorrect Instructions on
     Concurrent L2 and Northbridge Response

To generate a diff of this commit:
cvs rdiff -r1.23 -r1.24 src/sys/arch/x86/include/specialreg.h
cvs rdiff -r1.16 -r1.17 src/sys/arch/x86/x86/errata.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

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