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CVS commit: src/sys/arch/x86

Module Name:    src
Committed By:   cegger
Date:           Sun May 11 21:19:18 UTC 2008

Modified Files:
        src/sys/arch/x86/include: cacheinfo.h
        src/sys/arch/x86/x86: identcpu.c

Log Message:
print L3 and TLB cache information for AMD Barcelona/Phenom

To generate a diff of this commit:
cvs rdiff -r1.5 -r1.6 src/sys/arch/x86/include/cacheinfo.h
cvs rdiff -r1.3 -r1.4 src/sys/arch/x86/x86/identcpu.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

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