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Re: CVS commit: src/sys/arch
Andrew Doran wrote:
On Sat, May 10, 2008 at 06:36:08PM +0200, Christoph Egger wrote:
- When booting CPUs, detect TSC skew and account for it. Most Intel MP
systems have synchronized counters, but that need not be true if the
system has a complicated bus structure. As far as I know, AMD systems
do not have synchronized TSCs and so we need to handle skew.
This is true for AMD K8 (Family 0xf) and AMD Griffin (Family 0x11).
AMD Barcelona/Phenom (Family 0x10) synchronizes their TSC with the
memory clock which always runs at a fixed speed. On those systems you
need synchonrize the memory clock between the memory controller.
On each socket, there's one memory controller.
Presumably they will report TscInvariant
Right. CPUID 80000007, Bit 8 "TscInvariant".
> so it will be used there. What is the chance of drift between CPUs?
All CPU cores on one socket synchronize their TSC with the memory clock.
The synchronization is fully transparent to the OS.
The synchronization happens again and again, not only when p-state
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