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CVS commit: syssrc/sys/arch/sh5/sh5



Module Name:    syssrc
Committed By:   scw
Date:           Mon Aug 26 10:23:57 UTC 2002

Modified Files:
        syssrc/sys/arch/sh5/sh5: cpu_switch.S

Log Message:
- Add a debug check for SR.BL being set on entry to cpu_switch().
- Add sh5_savectx()
- Fix a branch target register botch in sh5_fpsave() and sh5_fprestore().


To generate a diff of this commit:
cvs rdiff -r1.4 -r1.5 syssrc/sys/arch/sh5/sh5/cpu_switch.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




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