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CVS commit: syssrc



Module Name:    syssrc
Committed By:   mrg
Date:           Mon Apr 10 16:05:13 UTC 2000

Modified Files:
        syssrc/sys/arch/sparc64/include: ctlreg.h

Log Message:
- IRSR_BUSY is bit 5 not bit 4.
- IRSR_MID(x) is &'d with 0x1f (5 bits) not 0xf.


To generate a diff of this commit:
cvs rdiff -r1.12 -r1.13 syssrc/sys/arch/sparc64/include/ctlreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




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