[src/trunk]: src/sys/arch/arm/cortex On secondary cores, invalidate the cache...

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/82f8a36a2f9e
branches:  trunk
changeset: 337921:82f8a36a2f9e
user:      matt <matt%NetBSD.org@localhost>
date:      Sun May 03 16:18:51 2015 +0000

description:
On secondary cores, invalidate the caches to make them clean.

diffstat:

 sys/arch/arm/cortex/a9_mpsubr.S |  16 +++++++++++++++-
 1 files changed, 15 insertions(+), 1 deletions(-)

diffs (30 lines):

diff -r 478094fa107a -r 82f8a36a2f9e sys/arch/arm/cortex/a9_mpsubr.S
--- a/sys/arch/arm/cortex/a9_mpsubr.S   Sun May 03 15:13:13 2015 +0000
+++ b/sys/arch/arm/cortex/a9_mpsubr.S   Sun May 03 16:18:51 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: a9_mpsubr.S,v 1.35 2015/04/27 07:13:44 skrll Exp $     */
+/*     $NetBSD: a9_mpsubr.S,v 1.36 2015/05/03 16:18:51 matt Exp $      */
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -538,6 +538,20 @@
        setend  be                              // switch to BE now
 #endif
 
+       // We haven't used anything from memory yet so we can invalidate the
+       // cache without fear of losing valuable data.  Note that the A5/A9
+       // L2 cache are not flushed via this call so this affects only this
+       // core's L1 cache.  The A7/A15/A17 L2 cache is write-through so
+       // invalidating it doesn't cause any data loss either.
+#if defined(KERNEL_BASES_EQUAL)
+       bl      _C_LABEL(armv7_dcache_inv_all)
+#else
+       movw    ip, #:lower16:_C_LABEL(armv7_dcache_inv_all)
+       movt    ip, #:upper16:_C_LABEL(armv7_dcache_inv_all)
+       sub     ip, ip, #KERNEL_BASE_VOFFSET
+       blx     ip                              // toss d-cache
+#endif
+
 #if 0
        mrc     p15, 0, r0, c1, c1, 2           // NSACR read
        // Allow non-secure access to ACTLR[SMP]