[src/trunk]: src/sys/arch/arm/allwinner add some PLL2 and APB0_GATING bits

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/e4d78d97a6b3
branches:  trunk
changeset: 331999:e4d78d97a6b3
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Thu Sep 04 02:35:26 2014 +0000

description:
add some PLL2 and APB0_GATING bits

diffstat:

 sys/arch/arm/allwinner/awin_reg.h |  8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diffs (25 lines):

diff -r ab114595f2a1 -r e4d78d97a6b3 sys/arch/arm/allwinner/awin_reg.h
--- a/sys/arch/arm/allwinner/awin_reg.h Thu Sep 04 02:34:32 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Thu Sep 04 02:35:26 2014 +0000
@@ -730,6 +730,12 @@
 #define AWIN_PLL1_SIG_DELT_PAT_IN      __BIT(3)
 #define AWIN_PLL1_SIG_DELT_PAT_EN      __BIT(2)
 
+#define AWIN_PLL2_CFG_PREVDIV          __BITS(4,0)
+#define AWIN_PLL2_CFG_FACTOR_N         __BITS(14,8)
+#define AWIN_PLL2_CFG_PLLBIAS          __BITS(20,16)
+#define AWIN_PLL2_CFG_VCOBIAS          __BITS(25,21)
+#define AWIN_PLL2_CFG_POSTDIV          __BITS(29,26)
+
 #define AWIN_PLL5_CFG_DDR_CLK_EN       __BIT(29)
 #define AWIN_PLL5_CFG_LDO_EN           __BIT(7)
 #define AWIN_PLL5_CFG_FACTOR_M1                __BITS(3,2)
@@ -817,6 +823,8 @@
 #define AWIN_APB_GATING1_TWI1          __BIT(1)
 #define AWIN_APB_GATING1_TWI0          __BIT(0)
 
+#define AWIN_APB0_GATING_ADDA          __BIT(0)
+
 #define AWIN_CLK_ENABLE                        __BIT(31)
 #define AWIN_CLK_SRC_SEL               __BITS(25,24)
 #define AWIN_CLK_SRC_SEL_OSC24M                0