Re: CVS commit: src/sys

[David Young <dyoung%pobox.com@localhost>]

On Sat, Aug 27, 2011 at 05:05:58PM +0000, Manuel Bouyer wrote:
> Module Name:  src
> Committed By: bouyer
> Date:         Sat Aug 27 17:05:58 UTC 2011
> 
> Modified Files:
>       src/sys/arch/evbmips/conf: LOONGSON
>       src/sys/conf: files
>       src/sys/dev/ata: ata_wdc.c
>       src/sys/dev/ic: wdc.c
> 
> Log Message:
> The loongon2f+cs5526+jmicron PATA->SATA bridge cause an interresting issue:
> 1) because the CS5536 is not associated with a x86 CPU, interrupts are not
>   ack'ed as it expects so interrupts cannot configured as edge-triggered
>   (as is expected for a PCIIDE in compat mode)
> 2) the PATA->SATA bridge ignores the WDC_IDS (interrupt disable bit) so
>   the PATA IRQ line gets asserted when resetting or running some polled
>   commands. It also wrongly asserts IRQ when the (nonexistent) slave
>   device is selected
> 2) wouldn't be an issue with edge-triggered interrupt because we would
>    get a spurious interrupt and continue operation, a new interrupt only shows
>    up when the PATA IRQ line goes low and high again. But because of 1),
>    we get an unclearable interrupt instead, and the system loops on the
>    interrupt handler.
> 
> To workaround this, introduce a WDC_NO_IDS compile option which runs
> all polled commands (including reset) at splbio() and without sleeps,
> so that the controller's interrupt is effectively disabled and
> won't be reenabled before the interrupt can be cleared.

ata_wdc.c does not compile if !WDC_NO_IDS because it contains:

+#ifdef WDC_NO_IDS
+       wait_flags = AT_POLL;
+#else
+#error "NEED WDC_NO_IDS"
+#endif

Dave

-- 
David Young             OJC Technologies
dyoung%ojctech.com@localhost      Urbana, IL * (217) 344-0444 x24