On 2021-07-07 20:02, Jason Thorpe wrote:
On Jul 7, 2021, at 8:41 AM, Johnny Billquist <bqt%update.uu.se@localhost> wrote: This might be extremely hard, since it's a feature that comes from the design of the PDP-11 MMU. The VAX MMU is very different, and don't allow this. (Allow might be the wrong word here - it's just not possible.) (Anyone talked about execute-only protection of memory... The PDP-11 have it. :-) )During the brainstorming of how to do a VAX-64 VM, I did mention that a split ITLB / DTLB would be useful for various reasons (and how it could be made "classical VAX-32" compatible), and so emulating a split I/D address space might be somewhat feasible on such a system.
It would be a nice addition. But it needs to be on the whole page table, and not just the TLB (I'm reading TLB as just the caching of (parts of) the page table here, but maybe you are thinking of something else?).
So - two page tables. One for I- and one for D-space.I wonder if there would be any bad effects of doing this? The PDP-11 also have separate page tables for the different processor modes, but I don't think that would be necessary. (Lots of page tables on a PDP-11... :-) )
Johnny
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