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New Vax - future directions :-)

So, some thought about expanding the Vax architecture.

For userspace; the vax architecture itself leave the door open for expanding the word size.   The instructions are all defined to use only the part of a register it needs, so adding a bunch of 'Q' instructions are a no-brainer.  Argument reference will work as before. The JMP/JSR/RET/... might need a Q counterpart, since it suddenly store/require 8 bytes instead of 4. Kernel; the hardware structures (SCB, PCB, ...) must all be expanded.  Memory management changed (but the existing leave much to wish for anyway).
All this is probably a quite simple update to the architecture.

IEEE floating point:
The current floating point formats are very like IEEE formats (compared to other pre-IEEE formats).  The F, G and H matches in layout the IEEE Single, Double and Extended but the exponent bias is slightly different and subnormal values are missing. By adding the three IEEE formats I think it would require very few extra gates to make it behave like the DEC FP instead.

Vax have had multiprocessor support since ~forever, but it may be a good idea to revise the interlock instructions.
There are only 7 of them and a few more would be nice.
Having it in a FPGA would make it simple to clone up many Vaxen in the same cheap chip :-)

Even though there are 288 instructions, a few are missing that would be nice.  For example;
- Unsigned mul/div.  Vax only have signed.
- logical shift right.  Vax have EXTZV, but it is an unneccessarily complicated instruction. - AND.  Vax have BIC instead, but that (almost) always require a complement as well.

-- R

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