Port-vax archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

Re: gcc vax bug in built-in ffs function/displacement indexed addressing

>>>              opcode startpos.rl, size.rb, base.vb, {field.rv}, findpos.wl

> The {field.rv} specifier appears to be a notational convention only
> standing for the three first operands,

Well, rather, I would say, standing for the bit-field described by the
first three operands.  It's the bit-field that's the conceptual
operand; the operands appearing in the assembly/machine code describe
the bit-field.  (To a certain extent, all operand specifiers merely
describe the operands, but, in the case of bit-fields, the description
is less direct than usual, combining multiple explicit operands into a
single implicit operand.)

> and does not appear as an actual instruction operand in assembly or
> disassembly.


> The document is lacking a description of this convention or at least
> I cannot find it either.

The first page of chapter 3 says, in part,

           2.  The format of each instruction  in  the  group.   The  format
               presents  the  name  and  type  of  each  instruction operand
               specifier and the  order  in  which  it  appears  in  memory.
               Operand  specifiers  from  left to right appear in increasing
               memory addresses.  Implied operands are enclosed by { }.

Page 2-19 also says

              The variable-length bit field instructions  treat  the
              position, size, and base address operand specifiers as
              the  specification  of  an   implied   field   operand

Searching for "implied" finds little other mention of implied operands;
almost all hits are in changelog entries.

/~\ The ASCII				  Mouse
\ / Ribbon Campaign
 X  Against HTML		mouse%rodents-montreal.org@localhost
/ \ Email!	     7D C8 61 52 5D E7 2D 39  4E F1 31 3E E8 B3 27 4B

Home | Main Index | Thread Index | Old Index