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Re: device matching at mainbus
Roger Ivie wrote:
> On Wed, 16 Jan 2013, Holm Tiffe wrote:
> >There are interrupt levels until 1F and each vector entry has 4 Bytes
> >(longword). Int 0 has an offset 0 in the SCB. IPL 14 which is needed for my
> >console driver has the possible Offsets of 0xF8,0xFC and 0x100.
> >How is this meant from the rtVAX Manual that the SCN should have an Vector
> >of 0x2c0 and an IPL 14? The VAX standard lists the Offset above 100 as
> >Implementaion-dependant...wich says nothing at all.
> I'm not sure what you're looking at (perhaps table 5-5 DEC Std 32?), but
> IPL is really independent of the vector. There is no requirement that any
> particular vector have any particular IPL.
Yes, table 5-5.
> For vectors F8 and FC, their talking about a standard console interface
> using the internal registers you would get at using MTPR/MFPR. You don't
> have such a console, so they are not relevant.
> Vectors 100-13C are typically used for IPL 14 vectors by a bus adapter
> like the UNIBUS adapter. This has nothing to do with your hardware.
> If your hardware implements a console interrupt, it will probably do
> so according to the VAXeln requirements, which would be an IPL 14
> interrupt with vector 0x2c0.
> roger ivie
I'm simply don't undestand the relationship between the IPL, the vector
and the address of the service routine.
Did you ment I can do an scb_vecalloc this way:
scb_vecalloc(0x2c0, (void (*)(void *)) scnintr, sc,
scb_vecalloc(int vecno, void (*func)(void *), void *arg,
int stack, struct evcnt *ev)
struct ivec_dsp *dsp = &scb_vec[vecno / 4];
dsp->hoppaddr = func;
dsp->pushlarg = arg;
dsp->ev = ev;
((intptr_t *) scb)[vecno/4] = (intptr_t)(dsp) | stack;
..that would allocate an vector entry at offset 0x2c0 in that table... and
the CPU is reading this vector when its IRQ0 is triggered?
from the RTVAX Manual (382ABUG2.PDF, that what you have on dead trees out
of the storage) page 3-14:
"...exept for console by devices emulating console storage and terminal
hardware. The console reserves vectors 02c0 to 02cc and interrupts at
IPL14 by means of IRQ<0> L."
Have I got it now right?
But since there are more vectors at that IPL14 how distinguishes the cpu
which vector to use?
For the SGEC the vector is written to the SGECs CSR0 register and somhow I
can understand that it is putting that vector on the bus if the CPU want's
to read it.. on the other side I've read that the VAX isn't doing this as
opposite to a PDP11.. that's my problem.
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