re: partially working SMP again

[matthew green <mrg%eterna.com.au@localhost>]

   I've tried the following ugly diff (I don't know about sparc MMU):

i don't really either.  and my sun4m documentation is 8000 miles
away in australi.  :-(

   ---
   Index: sparc/pmap.c
   ===================================================================
   RCS file: /cvsroot/src/sys/arch/sparc/sparc/pmap.c,v
   retrieving revision 1.329
   diff -u -r1.329 pmap.c
   --- sparc/pmap.c     27 May 2009 02:19:50 -0000      1.329
   +++ sparc/pmap.c     29 May 2009 12:39:12 -0000
   @@ -3814,7 +3814,7 @@
                paddr_t pa = PMAP_BOOTSTRAP_VA2PA(CPUINFO_VA + off);
                prom_printf("going to pmap_kenter_pa(va=%p, pa=%p)\n", va, pa);
                pmap_kremove(va, NBPG);
   -            pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
   +            pmap_kenter_pa(va, pa | PMAP_NC, VM_PROT_READ | VM_PROT_WRITE);
                cache_flush_page(va, 0);
                cache_flush_page(CPUINFO_VA, 0);
        }
   @@ -3833,6 +3833,9 @@
    #endif
    
        pmap_update(pmap_kernel());
   +    if (curcpu()->ci_self != cpus[0])
   +            prom_printf("curcpu()->ci_self = %p, cpus[0] = %p\n",
   +                curcpu()->ci_self, cpus[0]);
        prom_printf("pmap_bootstrap4m done\n");
    }
    
   @@ -3984,7 +3987,7 @@
                 ((u_long)pagtable_pa >> SRMMU_PPNPASHIFT) | SRMMU_TEPTD);
        setpgt4m(&pagtable[vpg],
                (VA2PA((void *)sc) >> SRMMU_PPNPASHIFT) |
   -            (SRMMU_TEPTE | PPROT_N_RWX | SRMMU_PG_C));
   +            (SRMMU_TEPTE | PPROT_N_RWX /*| SRMMU_PG_C*/));
    
        /* Install this CPU's context table */
        sc->ctx_tbl = ctxtable;
   
   ---


so, this leaves the original cpuinfo page cached.  you need to
modify the loop towards the end of pmap_bootstrap4m() so make
it skip SRMMU_PG_C for the CPUINFO_VA page.

i've tried a few different ideas of this without success.  

   > so i've spent a while looking at this just now.  the above should
   > really read "sparc_ncpus" without the -1.
   > 
   > i still haven't gotten this working.  i have gotten it to the
   > point where interrupts are enabled and it looks like cpu0_info->
   > intreg_4m is NULL, which is a symptom of failed flushes or so.
   > hmm...
   
   HyperSPARC has VIPT cache, so if we need to map one PA page
   against multiple VAs, all the VAs should have the same VA indexes
   to avoid virtual cache aliases.
   
   I guess sparc/cpu.c:alloc_cpuinfo_gloval_va() in 4.0 handles it.

ah, that's what the align variable is used for i guess.  i'll
fiddle around with making sure these are laid out properly..

i don't have a hypersparc system handy any more.


.mrg.