Re: partially working SMP again

[Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>]

>       > An easy check is to add this at the end of pmap_bootstrap4m:
>       > 
>       >         if (curcpu()->ci_self != cpus[0])
>       >                 panic("cpuinfo inconsistent");
>       
>       This test fails on my SS20MP.
>       
>       Using PMAP_NC on remapping cpuinfo_data and removing SRMMU_PG_C
>       on CPUINFO_VA mappings seems to fix the inconsistency (alias problem?),
>       though it still fails later:
>    
>    hmm.. what about removing the cache bit on the rest of the
>    cpuinfo_data mappings?  the ones from cpuinfo_data + cpuinfo_len
>    to cpuinfo_data + (cpuinfo_len * (sparc_ncpus-1)).

I've tried the following ugly diff (I don't know about sparc MMU):
---
Index: sparc/pmap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc/sparc/pmap.c,v
retrieving revision 1.329
diff -u -r1.329 pmap.c
--- sparc/pmap.c        27 May 2009 02:19:50 -0000      1.329
+++ sparc/pmap.c        29 May 2009 12:39:12 -0000
@@ -3814,7 +3814,7 @@
                paddr_t pa = PMAP_BOOTSTRAP_VA2PA(CPUINFO_VA + off);
                prom_printf("going to pmap_kenter_pa(va=%p, pa=%p)\n", va, pa);
                pmap_kremove(va, NBPG);
-               pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
+               pmap_kenter_pa(va, pa | PMAP_NC, VM_PROT_READ | VM_PROT_WRITE);
                cache_flush_page(va, 0);
                cache_flush_page(CPUINFO_VA, 0);
        }
@@ -3833,6 +3833,9 @@
 #endif
 
        pmap_update(pmap_kernel());
+       if (curcpu()->ci_self != cpus[0])
+               prom_printf("curcpu()->ci_self = %p, cpus[0] = %p\n",
+                   curcpu()->ci_self, cpus[0]);
        prom_printf("pmap_bootstrap4m done\n");
 }
 
@@ -3984,7 +3987,7 @@
                 ((u_long)pagtable_pa >> SRMMU_PPNPASHIFT) | SRMMU_TEPTD);
        setpgt4m(&pagtable[vpg],
                (VA2PA((void *)sc) >> SRMMU_PPNPASHIFT) |
-               (SRMMU_TEPTE | PPROT_N_RWX | SRMMU_PG_C));
+               (SRMMU_TEPTE | PPROT_N_RWX /*| SRMMU_PG_C*/));
 
        /* Install this CPU's context table */
        sc->ctx_tbl = ctxtable;

---


> so i've spent a while looking at this just now.  the above should
> really read "sparc_ncpus" without the -1.
> 
> i still haven't gotten this working.  i have gotten it to the
> point where interrupts are enabled and it looks like cpu0_info->
> intreg_4m is NULL, which is a symptom of failed flushes or so.
> hmm...

HyperSPARC has VIPT cache, so if we need to map one PA page
against multiple VAs, all the VAs should have the same VA indexes
to avoid virtual cache aliases.

I guess sparc/cpu.c:alloc_cpuinfo_gloval_va() in 4.0 handles it.
---
Izumi Tsutsui