Re: state of riscv?

[Zach McGrew <zmcgrew%gmail.com@localhost>]

Hi everybody,

My code for RISC-V is in my GitHub fork [1]. I had started putting
together a big diff for Maxime last year, and decided to rebase it on a
newer -current. This caused some issues since the github mirror history
goes crazy occasionally -- Life happened, and this kinda fell to the
wayside.

I still hack on it from time to time, but haven't made much
progress. After speaking with some people at BSDCan 2019 they suggested
I look into using Qemu instead of Spike, so I've started down that path,
but haven't spent enough time to get very far. I had a disk that failed
back in ~March of this year and lost the build script I had to automate
the extra steps needed at the end of building the kernel. My memory is a
little fuzzy on this, but I believe the script built the kernel with the
MD that contained the userland, and wrapped the kernel with BBL (the
Berkley Boot Loader [2]) so that the SBI was available. Loading it into
Spike would boot up to around execing init. I seem to recall there was
an issue with interrupts?

I'll try and sink some time into it this weekend so I can at least
finally get Maxime the diff. Maybe we can setup a branch in cvs to make
it a bit easier to all coordinate on.

-Zach

Reference URLs:
1. https://github.com/zmcgrew/src
2. https://github.com/riscv/riscv-pk/