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Re: Interrupt handling and routing: The Big Picture
On Mar 13, 2012, at 7:49 AM, Michael wrote:
> On Tue, 13 Mar 2012 14:36:00 +0100
> Frank Wille <frank%phoenix.owl.de@localhost> wrote:
>>>> Maybe newer CPUs with critical interrupts should be handled like in
>>>> powerpc/booke/e500_intr.c ?
>>> Well. It looks like I can programm the PIC so that it only generates
>>> standard interrupts...
>> Hm. Really? I had a glance at the interrupt routing diagram in the UM
>> yesterday, and it looked like some devices can only deliver critial
> You can always have several exceptions trigger the same PIC and have your
> driver figure out which one it was.
Bit CEb in ICTL External Enable and External Types Register:
Critical Enable—a special control bit, which if set, directs critical interrupt
sources to the normal core Interrupt pin. This is for system programmer who
prefers to handle all interrupts in a single ISR.
The status operation remains unchanged, it is necessary to parse Critical
Status information prior to Normal Status information to detect critical
interrupt sources routed to the normal interrupt pin.
>>> Yes. But the hwirq is just an int number. The MPC5200 PIC has four
>>> types of interrupts: Peripheral, External, Main and BestComm. All
>>> these interrupts are numbered starting at 0. So I have to do some
>>> things like: hwirq 0..31 is External, 32..63 is Main, 64..95 is
>>> Peripheral, 96..112 is BestComm. At least the OpenFirmWare seems to
>>> do something like this. [...]
>> Yes. You can use any hwirq number you like. Just your PIC driver needs
>> to perform the right actions on it.
> Indeed, the hwirq number in this context is nothing but a single number to
> identify an interrupt, it doesn't need to have anything to do with actual
> Jochen - for a simple PIC driver just look at macppc's Heathrow or Ohare (
> arch/macppc/macppc/pic_heathrow.c and pic_ohare.c ) - the 'interrupt
> controller' there is nothing but a handful bitmapped registers to enable,
> clear and check status on a bunch of interrupt lines.
> The reason why the interrupt code looks like this is the fact that there are
> many powerpc boxes with several cascaded interrupt controllers ( examples:
> the powerbook 3400 has two ohares, some ofppc and prep boxes have i8259
> cascaded with IVRs or OpenPICs and so on ), this way we can set up each one
> separately and then wire them together as needed ( and that's why each one
> has a number range, so the hwirq number is not per pic but per pic tree )
I also recently moved the ibm4xx to use pic and its PIC is similar and
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