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Re: Show stopper bugs for 5.0
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On May 21, 2008, at 16:54, Manuel Bouyer wrote:
On Wed, May 21, 2008 at 04:40:06PM -0400, Michael Lorenz wrote:
On May 21, 2008, at 15:43, Manuel Bouyer wrote:
On Tue, May 20, 2008 at 08:39:09PM -0400, Michael Lorenz wrote:
I didn't commit the fix yet because chuq thinks that's just a
workaround for a problem elsewhere, but I couldn't find anything
remotely related in the 7400 errata list. He's got a dual 7455
doesn't have this problem - his CPUs have L3 cache though, no
Maybe it's L1 cache have different characteristics ?
Both have 32kB instruction and 32kB data cache.
Could it happen that this part of code has already been cached in
L1 instruction cache at this point of operations, but not on
As far as I know the L1 caches should behave identical on both CPUs.
Do you know the line size and associativity ?
Both L1 caches are 32-byte line, 8-way set associative on both the
7400 and 7455.
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