Re: mipsX_subr.S:tlb_invalid_exception

[Masao Uebayashi <uebayasi%gmail.com@localhost>]

http://mail-index.netbsd.org/port-mips/2002/11/17/0005.html

According to this, the G bit is nothing to do with "wiring".

I also wonder how the wired bit in pte is used in mips.

On Sat, Oct 1, 2011 at 11:41 PM, Masao Uebayashi <uebayasi%gmail.com@localhost> 
wrote:
> In the following code:
>
> 1693         bnez    k0, MIPSX(kern_tlbi_odd)
> 1694          nop
> 1695
> 1696         INT_L   k0, 0(k1)                       # get PTE entry
> 1697         _SLL    k0, k0, WIRED_SHIFT             # get rid of "wired" bit
> 1698         _SRL    k0, k0, WIRED_SHIFT
> 1699         _MTC0   k0, MIPS_COP_0_TLB_LO0          # load PTE entry
> 1700         COP0_SYNC
> 1701         and     k0, k0, MIPS3_PG_V              # check for valid entry
> 1702 #ifdef MIPS3
> 1703         nop                                     # required for QED5230
> 1704 #endif
> 1705         beqz    k0, _C_LABEL(MIPSX(kern_gen_exception)) # PTE invalid
> 1706          nop                                    # - delay slot -
>
> - Why load PTE before checking V bit?  If invalid,
> kern_gen_exception() will load PTE later (uvm_fault() -> pmap_enter()
> -> tlb_update()), right?
>
> 1708         INT_L   k0, 4(k1)                       # get odd PTE entry
> 1709         _SLL    k0, k0, WIRED_SHIFT
> 1710         mfc0    k1, MIPS_COP_0_TLB_INDEX
> 1711         _SRL    k0, k0, WIRED_SHIFT
> 1712         sltiu   k1, k1, MIPS3_TLB_WIRED_UPAGES  # Luckily this is
> MIPS3_PG_G
> 1713         or      k1, k1, k0
> 1714         _MTC0   k0, MIPS_COP_0_TLB_LO1          # load PTE entry
> 1715         COP0_SYNC
>
> - Line 1712 + 1713 sets and ORs a value into k1, but it's unused.  Is
> it intended?
>
> - Why trying to set G bit only in LO1?  According to [1], LO0:G and
> LO1:G are AND'ed.
>
> [1] MIPS32™ Architecture For Programmers Volume III: The MIPS32™
> Privileged Resource Architecture
>