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mips changes for loongson2
Hello,
my work on getting the lemote fuloong working is almost ready to
be commited (it'll be another evbmips sub-port: evbmips/loongson,
which should also work on the lebote yeloong, the gdium and probably others).
This requires a few changes to some mips-specific files as in the attached
patches:
- bonito.diff:
make the 'struct bonito_config' const, so that it can be in kernel
text instead of data. This needs some __UNCONST() but I guess
it's no big deal.
Add a bc_attach_hook to struct bonito_config, to be used as pc_attach_hook
if not NULL.
Add some LS2-specific register defines (LS2f uses a modified bonito64).
- mips.diff:
add some LS2F specific defines to cpuregs.h
Fix a bug with VM_MAXUSER_ADDRESS and 16k pages (VM_MAXUSER_ADDRESS
doens't change with page size ...)
Hack some assembly files for LS2 branch prediction bug workaround on
j(r) reg, as already discussed here (basically, the assembler needs to
be able to use at register when it runs into a j register instruction).
LS2-specific tlbmiss handler (ls2 doesn't have a separate handler for
64bit addresses)
Fixes for some #ifdef MIPS3_LOONGSON2 assembly code (using the wrong
register).
mips_fixup.c: add code to handle the instructions added by
-fix-loongson2-btb
- common.diff:
Hack some assembly files for LS2 branch prediction bug workaround on
j(r) reg when used in kernel code by allowing at use where needed.
- binutils.diff: add fix-loongson2f-btb option to gas, from openbsd.
This works around a bug in the branch target buffer of the CPU, which may
cause it to fetch instructions at the wrong place and cause the platform
to deadlock. This works around the same bug as fix-loongson2f-jump,
but in a different way (force a BTB clear through a write to cop0, while
fix-loongson2f-jump silently changes the jump address which can cause
various problems).
Unless someone object, I'll commit this in a few days.
--
Manuel Bouyer <bouyer%antioche.eu.org@localhost>
NetBSD: 26 ans d'experience feront toujours la difference
--
Index: dist/gas/config/tc-mips.c
===================================================================
RCS file: /cvsroot/src/external/gpl3/binutils/dist/gas/config/tc-mips.c,v
retrieving revision 1.5
diff -u -p -u -r1.5 tc-mips.c
--- dist/gas/config/tc-mips.c 18 Aug 2011 06:32:35 -0000 1.5
+++ dist/gas/config/tc-mips.c 24 Aug 2011 17:28:10 -0000
@@ -778,6 +778,8 @@ static int mips_fix_vr4130;
efficient expansion. */
static int mips_relax_branch;
+
+static int mips_fix_loongson2f_btb;
/* The expansion of many macros depends on the type of symbol that
they refer to. For example, when generating position-dependent code,
@@ -1051,6 +1053,7 @@ static void macro_build (expressionS *,
static void mips16_macro_build
(expressionS *, const char *, const char *, va_list);
static void load_register (int, expressionS *, int);
+static void macro_build (expressionS *, const char *, const char *, ...);
static void macro_start (void);
static void macro_end (void);
static void macro (struct mips_cl_insn * ip);
@@ -3584,6 +3587,41 @@ macro_read_relocs (va_list *args, bfd_re
r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
}
+/* Fix jump through register issue on loongson2f processor for kernel code:
+ force a BTB clear before the jump to prevent it from being incorrectly
+ prefetched by the branch prediction engine. */
+
+static void
+macro_build_jrpatch (expressionS *ep, unsigned int sreg)
+{
+ if (!mips_fix_loongson2f_btb)
+ return;
+
+ if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == AT)
+ return;
+
+ if (!mips_opts.at)
+ {
+ as_warn (_("unable to apply loongson2f BTB workaround when .set noat"));
+ return;
+ }
+
+ /* li $at, COP_0_BTB_CLEAR | COP_0_RAS_DISABLE */
+ ep->X_op = O_constant;
+ ep->X_add_number = 3;
+ macro_build (ep, "ori", "t,r,i", AT, ZERO, BFD_RELOC_LO16);
+
+ /* dmtc0 $at, COP_0_DIAG */
+ macro_build (NULL, "dmtc0", "t,G", AT, 22);
+
+ /* Hide these two instructions to avoid getting a ``macro expanded into
+ multiple instructions'' warning. */
+ if (mips_relax.sequence != 2)
+ mips_macro_warning.sizes[0] -= 2 * 4;
+ if (mips_relax.sequence != 1)
+ mips_macro_warning.sizes[1] -= 2 * 4;
+}
+
/* Build an instruction created by a macro expansion. This is passed
a pointer to the count of instructions created so far, an
expression, the name of the instruction to build, an operand format
@@ -3985,6 +4023,7 @@ macro_build_jalr (expressionS *ep)
frag_grow (8);
f = frag_more (0);
}
+ macro_build_jrpatch (ep, PIC_CALL_REG);
macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
if (HAVE_NEWABI)
fix_new_exp (frag_now, f - frag_now->fr_literal,
@@ -6167,6 +6206,26 @@ macro (struct mips_cl_insn *ip)
/* AT is not used, just return */
return;
+ case M_JR_S:
+ macro_build_jrpatch (&expr1, sreg);
+ macro_build (NULL, "jr", "s", sreg);
+ return; /* didn't modify $at */
+
+ case M_J_S:
+ macro_build_jrpatch (&expr1, sreg);
+ macro_build (NULL, "j", "s", sreg);
+ return; /* didn't modify $at */
+
+ case M_JALR_S:
+ macro_build_jrpatch (&expr1, sreg);
+ macro_build (NULL, "jalr", "s", sreg);
+ return; /* didn't modify $at */
+
+ case M_JALR_DS:
+ macro_build_jrpatch (&expr1, sreg);
+ macro_build (NULL, "jalr", "d,s", dreg, sreg);
+ return; /* didn't modify $at */
+
case M_J_A:
/* The j instruction may not be used in PIC code, since it
requires an absolute address. We convert it to a b
@@ -6185,12 +6244,16 @@ macro (struct mips_cl_insn *ip)
/* Fall through. */
case M_JAL_2:
if (mips_pic == NO_PIC)
- macro_build (NULL, "jalr", "d,s", dreg, sreg);
+ {
+ macro_build_jrpatch (&expr1, sreg);
+ macro_build (NULL, "jalr", "d,s", dreg, sreg);
+ }
else
{
if (sreg != PIC_CALL_REG)
as_warn (_("MIPS PIC call to register other than $25"));
+ macro_build_jrpatch (&expr1, sreg);
macro_build (NULL, "jalr", "d,s", dreg, sreg);
if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
{
@@ -11324,9 +11387,14 @@ struct option md_longopts[] =
#define OPTION_NO_FIX_LOONGSON2F_NOP (OPTION_FIX_BASE + 9)
{"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
{"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
+#define OPTION_FIX_LOONGSON2F_BTB (OPTION_FIX_BASE + 10)
+#define OPTION_NO_FIX_LOONGSON2F_BTB (OPTION_FIX_BASE + 11)
+ {"mfix-loongson2f-btb", no_argument, NULL, OPTION_FIX_LOONGSON2F_BTB},
+ {"mno-fix-loongson2f-btb", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_BTB},
+
/* Miscellaneous options. */
-#define OPTION_MISC_BASE (OPTION_FIX_BASE + 10)
+#define OPTION_MISC_BASE (OPTION_FIX_BASE + 12)
#define OPTION_TRAP (OPTION_MISC_BASE + 0)
{"trap", no_argument, NULL, OPTION_TRAP},
{"no-break", no_argument, NULL, OPTION_TRAP},
@@ -11645,6 +11713,14 @@ md_parse_option (int c, char *arg)
mips_fix_vr4130 = 0;
break;
+ case OPTION_FIX_LOONGSON2F_BTB:
+ mips_fix_loongson2f_btb = 1;
+ break;
+
+ case OPTION_NO_FIX_LOONGSON2F_BTB:
+ mips_fix_loongson2f_btb = 0;
+ break;
+
case OPTION_RELAX_BRANCH:
mips_relax_branch = 1;
break;
@@ -15590,6 +15666,7 @@ MIPS options:\n\
-mfix-loongson2f-nop work around Loongson2F NOP errata\n\
-mfix-vr4120 work around certain VR4120 errata\n\
-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
+-mfix-loongson2f-btb work around Loongson2F BTB errata\n\
-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
-msym32 assume all symbols have 32-bit values\n\
Index: dist/gas/doc/c-mips.texi
===================================================================
RCS file: /cvsroot/src/external/gpl3/binutils/dist/gas/doc/c-mips.texi,v
retrieving revision 1.3
diff -u -p -u -r1.3 c-mips.texi
--- dist/gas/doc/c-mips.texi 14 Apr 2011 07:49:48 -0000 1.3
+++ dist/gas/doc/c-mips.texi 24 Aug 2011 17:28:11 -0000
@@ -182,6 +182,14 @@ all problems in hand-written assembler c
@itemx -no-mfix-vr4130
Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
+@item -mfix-loongson2f-btb
+@itemx -mno-fix-loongson2f-btb
+Clear the Branch Target Buffer before any jump through a register. This
+option is intended to be used on kernel code for the Loongson 2F processor
+only; userland code compiled with this option will fault, and kernel code
+compiled with this option run on another processor than Loongson 2F will
+yield unpredictable results.
+
@item -m4010
@itemx -no-m4010
Generate code for the LSI @sc{r4010} chip. This tells the assembler to
Index: dist/include/opcode/mips.h
===================================================================
RCS file: /cvsroot/src/external/gpl3/binutils/dist/include/opcode/mips.h,v
retrieving revision 1.3
diff -u -p -u -r1.3 mips.h
--- dist/include/opcode/mips.h 2 Aug 2011 16:11:17 -0000 1.3
+++ dist/include/opcode/mips.h 24 Aug 2011 17:28:12 -0000
@@ -762,7 +762,11 @@ enum
M_DSUB_I,
M_DSUBU_I,
M_DSUBU_I_2,
+ M_JR_S,
+ M_J_S,
M_J_A,
+ M_JALR_S,
+ M_JALR_DS,
M_JAL_1,
M_JAL_2,
M_JAL_A,
Index: dist/opcodes/mips-opc.c
===================================================================
RCS file: /cvsroot/src/external/gpl3/binutils/dist/opcodes/mips-opc.c,v
retrieving revision 1.5
diff -u -p -u -r1.5 mips-opc.c
--- dist/opcodes/mips-opc.c 14 Apr 2011 08:05:00 -0000 1.5
+++ dist/opcodes/mips-opc.c 24 Aug 2011 17:28:13 -0000
@@ -712,10 +712,12 @@ const struct mips_opcode mips_builtin_op
{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0,
I2 },
{"hibernate","", 0x42000023, 0xffffffff, 0,
0, V1 },
{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,
0, I33 },
+{"jr", "s", 0, (int) M_JR_S, INSN_MACRO, 0,
I1 },
{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0,
I1 },
/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
the same hazard barrier effect. */
{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0,
I32 },
+{"j", "s", 0, (int) M_J_S, INSN_MACRO, 0,
I1 },
{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0,
I1 }, /* jr */
/* SVR4 PIC code requires special handling for j, so it must be a
macro. */
@@ -724,7 +726,9 @@ const struct mips_opcode mips_builtin_op
assembler, but will never match user input (because the line above
will match first). */
{"j", "a", 0x08000000, 0xfc000000, UBD, 0,
I1 },
+{"jalr", "s", 0, (int) M_JALR_S, INSN_MACRO, 0,
I1 },
{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0,
I1 },
+{"jalr", "d,s", 0, (int) M_JALR_DS, INSN_MACRO, 0,
I1 },
{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0,
I1 },
/* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
with the same hazard barrier effect. */
Index: include/cpuregs.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/cpuregs.h,v
retrieving revision 1.85
diff -u -p -u -r1.85 cpuregs.h
--- include/cpuregs.h 2 Aug 2011 05:12:32 -0000 1.85
+++ include/cpuregs.h 24 Aug 2011 17:21:23 -0000
@@ -1,6 +1,22 @@
/* $NetBSD: cpuregs.h,v 1.85 2011/08/02 05:12:32 matt Exp $ */
/*
+ * Copyright (c) 2009 Miodrag Vallat.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
@@ -970,4 +986,45 @@
#include <mips/rmi/rmixlreg.h>
#endif
+#ifdef MIPS3_LOONGSON2
+/*
+ * Loongson 2E/2F specific defines
+ */
+
+/*
+ * Address Window registers physical addresses
+ *
+ * The Loongson 2F processor has an AXI crossbar with four possible bus
+ * masters, each one having four programmable address windows.
+ *
+ * Each window is defined with three 64-bit registers:
+ * - a base address register, defining the address in the master address
+ * space (base register).
+ * - an address mask register, defining which address bits are valid in this
+ * window. A given address matches a window if (addr & mask) == base.
+ * - the location of the window base in the target, as well at the target
+ * number itself (mmap register). The lower 20 bits of the address are
+ * forced as zeroes regardless of their value in this register.
+ * The translated address is thus (addr & ~mask) | (mmap & ~0xfffff).
+ */
+
+#define LOONGSON_AWR_BASE_ADDRESS 0x3ff00000ULL
+
+#define LOONGSON_AWR_BASE(master, window) \
+ (LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x00)
+#define LOONGSON_AWR_SIZE(master, window) \
+ (LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x20)
+#define LOONGSON_AWR_MMAP(master, window) \
+ (LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x40)
+
+/*
+ * Bits in the diagnostic register
+ */
+
+#define COP_0_DIAG_ITLB_CLEAR 0x04
+#define COP_0_DIAG_BTB_CLEAR 0x02
+#define COP_0_DIAG_RAS_DISABLE 0x01
+
+#endif /* MIPS3_LOONGSON2 */
+
#endif /* _MIPS_CPUREGS_H_ */
Index: include/vmparam.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/vmparam.h,v
retrieving revision 1.49
diff -u -p -u -r1.49 vmparam.h
--- include/vmparam.h 21 Jul 2011 23:03:39 -0000 1.49
+++ include/vmparam.h 24 Aug 2011 17:21:23 -0000
@@ -155,7 +155,11 @@
*/
#define VM_MIN_ADDRESS ((vaddr_t)0x00000000)
#ifdef _LP64
+#if 0
#define VM_MAXUSER_ADDRESS ((vaddr_t) 1L << (4*PGSHIFT-8))
+#else
+#define VM_MAXUSER_ADDRESS ((vaddr_t) 1L << (40))
+#endif
/* 0x0000010000000000 */
#define VM_MAX_ADDRESS VM_MAXUSER_ADDRESS
#define VM_MIN_KERNEL_ADDRESS ((vaddr_t) 3L << 62) /* 0xC000000000000000 */
Index: mips/lock_stubs_ras.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/lock_stubs_ras.S,v
retrieving revision 1.3
diff -u -p -u -r1.3 lock_stubs_ras.S
--- mips/lock_stubs_ras.S 29 Apr 2011 22:04:42 -0000 1.3
+++ mips/lock_stubs_ras.S 24 Aug 2011 17:21:23 -0000
@@ -81,6 +81,20 @@
.set noat
/*
+ * to work around the branch prediction engine misbehavior of
+ * Loongson 2F processors we need to clear the branch target buffer before
+ * a j ra. This requires extra instructions which don't fit in the RAS blocks,
+ * so do a PC-relative just to a block of code (this is the same size as
+ * a j ra) where we can let the assembler install the workaround.
+ */
+#ifdef MIPS3_LOONGSON2F
+#define J_RA j loongson_return
+#else
+#define J_RA j ra
+#endif
+
+
+/*
* unsigned long ras_atomic_cas_ulong(volatile unsigned long *val,
* unsigned long old, unsigned long new);
*/
@@ -89,7 +103,7 @@
EXPORT(_lock_ras_start)
STATIC_LEAF(ras_atomic_cas_noupdate)
- j ra
+ J_RA
move v0, t0
END(ras_atomic_cas_noupdate)
@@ -105,7 +119,7 @@ _atomic_cas_ulong_ras_start:
nop
PTR_S a2, (a0) /* <- critical section end */
_atomic_cas_ulong_ras_end:
- j ra
+ J_RA
move v0, a1
END(ras_atomic_cas_ulong)
@@ -125,7 +139,7 @@ _atomic_cas_uint_ras_start:
nop
INT_S a2, (a0) /* <- critical section end */
_atomic_cas_uint_ras_end:
- j ra
+ J_RA
move v0, a1
END(ras_atomic_cas_uint)
@@ -146,7 +160,7 @@ _ucas_ulong_ras_start:
LONG_S a2, (a0) /* <- critical section end */
_ucas_ulong_ras_end:
PTR_S zero, PCB_ONFAULT(v1)
- j ra
+ J_RA
LONG_S t0, 0(a3)
END(_ucas_ulong_ras)
@@ -165,7 +179,7 @@ _ucas_uint_ras_start:
INT_S a2, (a0) /* <- critical section end */
_ucas_uint_ras_end:
PTR_S zero, PCB_ONFAULT(v1)
- j ra
+ J_RA
INT_S t0, 0(a3)
END(_ucas_uint_ras)
@@ -184,7 +198,7 @@ _mutex_enter_ras_start:
nop
PTR_S MIPS_CURLWP, (a0)/* <- critical section end */
_mutex_enter_ras_end:
- j ra
+ J_RA
nop
END(ras_mutex_enter)
@@ -203,7 +217,7 @@ _mutex_exit_ras_start:
nop
PTR_S zero, (a0) /* <- critical section end */
_mutex_exit_ras_exit:
- j ra
+ J_RA
nop
END(ras_mutex_exit)
@@ -223,6 +237,13 @@ END(ras_mutex_vector_exit)
.p2align LOG2_MIPS_LOCK_RAS_SIZE /* Get out of the RAS block */
+ .set at
+#ifdef MIPS3_LOONGSON2F
+loongson_return:
+ j ra
+ nop
+#endif
+
/*
* Patch up the given address. We arrive here if we might have trapped
* within one of the critical sections above. Do:
Index: mips/mipsX_subr.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/mipsX_subr.S,v
retrieving revision 1.53
diff -u -p -u -r1.53 mipsX_subr.S
--- mips/mipsX_subr.S 16 Aug 2011 06:55:12 -0000 1.53
+++ mips/mipsX_subr.S 24 Aug 2011 17:21:23 -0000
@@ -330,8 +330,54 @@
*
* Don't check for invalid pte's here. We load them as well and
* let the processor trap to load the correct value after service.
+ *
+ * Loongson2 processors don't have separate tlbmiss and xtlbmiss handlers;
+ * so we have to check for useg addresses in tlb_miss. The good news is that
+ * we can use 64 intructions form tlbmiss instead of 32.
+ *
*----------------------------------------------------------------------------
*/
+#ifdef MIPS3_LOONGSON2
+/* this loongson2-specific part is almost a copy of xtlb_miss */
+VECTOR(MIPSX(tlb_miss), unknown)
+ .set noat
+ dmfc0 k0, MIPS_COP_0_BAD_VADDR #00: k0=bad address
+#ifdef _LP64
+ nop #01: nop
+ bltz k0, MIPSX(kernelfault) #02: k0<0 -> kernel fault
+ PTR_SRL k1, k0, 31 #03: clear useg bits
+ beqz k1, 1f #04: k1==0 -> useg address
+ PTR_SRL k1,k0,2*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2)+PGSHIFT #05:
clear valid bits
+ bnez k1, MIPSX(nopagetable) #06: not legal address
+ PTR_SRL k0, 2*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2) #05: k0=seg offset
(almost)
+ lui k1, %hi(CPUVAR(PMAP_SEGTAB)) #07: k1=hi of segtab
+ andi k0, NBPG-(1<<PTR_SCALESHIFT) #08: k0=seg offset (mask 0x3)
+ PTR_L k1, %lo(CPUVAR(PMAP_SEGTAB))(k1)#09: k1=segment tab
+ PTR_ADDU k1, k0 #0a: k1=seg entry address
+ dmfc0 k0, MIPS_COP_0_BAD_VADDR #0b: k0=bad address (again)
+ PTR_L k1, 0(k1) #0c: k1=seg entry
+ b MIPSX(tlb_miss_common) #0d
+ PTR_SRL k0, 1*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2) #0e: k0=seg offset
(almost)
+#endif /* LP64 */
+1: /* handle useg addresses */
+ lui k1, %hi(CPUVAR(PMAP_SEG0TAB)) #0f: k1=hi of seg0tab
+ bltz k0, MIPSX(kernelfault) #10: k0<0 -> kernel fault
+ dsrl k0, 31 #11: clear low 31 bits
+ bnez k0, MIPSX(nopagetable) #12: not legal address
+ PTR_L k1, %lo(CPUVAR(PMAP_SEG0TAB))(k1)#13: k1=segment tab base
+ dmfc0 k0, MIPS_COP_0_BAD_VADDR #14: k0=bad address (again)
+ nop #15
+ b MIPSX(tlb_miss_common) #16
+ PTR_SRL k0, 1*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2) #17: k0=seg offset
(almost)
+_VECTOR_END(MIPSX(tlb_miss))
+/* dummy xtlb_miss (also a placeholder for tlb_miss_common) */
+VECTOR(MIPSX(xtlb_miss), unknown)
+ lui k0, %hi(_C_LABEL(panic)) #00
+ addiu k0, %lo(_C_LABEL(panic)) #01
+ lui a0, %hi(loongson2_xtlb_miss_str) #02
+ jr k0 #03
+ addiu a0, %lo(loongson2_xtlb_miss_str) #04
+#else /* !MIPS3_LOONGSON2 */
VECTOR(MIPSX(tlb_miss), unknown)
.set noat
#ifdef MIPS3_LOONGSON2
@@ -343,6 +389,7 @@ VECTOR(MIPSX(tlb_miss), unknown)
bltz k0, MIPSX(kernelfault) #02: k0<0 -> 4f (kernel fault)
PTR_SRL k0, 1*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2)#03: k0=seg offset
(almost)
PTR_L k1, %lo(CPUVAR(PMAP_SEG0TAB))(k1)#04: k1=seg0tab
+#endif /* !MIPS3_LOONGSON2 */
MIPSX(tlb_miss_common):
#ifdef _LP64
beqz k1, MIPSX(nopagetable) #05: is there a pagetable?
@@ -380,8 +427,13 @@ MIPSX(tlb_miss_common):
#endif
eret #1f: return from exception
.set at
+#ifdef MIPS3_LOONGSON2
+_VECTOR_END(MIPSX(xtlb_miss))
+#else
_VECTOR_END(MIPSX(tlb_miss))
+#endif
+#ifndef MIPS3_LOONGSON2
#if defined(USE_64BIT_CP0_FUNCTIONS)
/*
* mipsN_xtlb_miss routine
@@ -397,6 +449,9 @@ _VECTOR_END(MIPSX(tlb_miss))
*
* Don't check for invalid pte's here. We load them as well and
* let the processor trap to load the correct value after service.
+ *
+ * Loongson2 CPUs don't have separate tlbmiss and xtlbmiss, so we have
+ * to check the address size here and branch to tlb_miss if needed.
*/
VECTOR(MIPSX(xtlb_miss), unknown)
.set noat
@@ -429,6 +484,7 @@ _VECTOR_END(MIPSX(xtlb_miss))
#else
.space 128
#endif /* USE_64BIT_CP0_FUNCTIONS */
+#endif /* !MIPS3_LOONGSON2 */
/*
* Vector to real handler in KSEG1.
@@ -1431,6 +1487,7 @@ NESTED_NOPROFILE(MIPSX(systemcall), CALL
/*
* Call the system call handler.
*/
+ .set at
jalr t9
move a0, MIPS_CURLWP # 1st arg is curlwp
@@ -1446,7 +1503,6 @@ NESTED_NOPROFILE(MIPSX(systemcall), CALL
lui ra, %hi(MIPSX(user_return)) # return directly to user return
j _C_LABEL(ast)
PTR_ADDIU ra, %lo(MIPSX(user_return)) # return directly to user return
- .set at
END(MIPSX(systemcall))
/*
@@ -1716,6 +1772,8 @@ END(MIPSX(tlb_invalid_exception))
.globl _C_LABEL(MIPSX(exceptionentry_end))
_C_LABEL(MIPSX(exceptionentry_end)):
+ .set at
+
/*--------------------------------------------------------------------------
*
* mipsN_tlb_set_asid --
@@ -1784,8 +1842,8 @@ LEAF(MIPSX(tlb_update))
tlbwi # update slot found
COP0_SYNC
#ifdef MIPS3_LOONGSON2
- li k0, MIPS_DIAG_ITLB_CLEAR
- mtc0 v0, MIPS_COP_0_DIAG # invalidate ITLB
+ li t1, MIPS_DIAG_ITLB_CLEAR
+ mtc0 t1, MIPS_COP_0_DIAG # invalidate ITLB
#elif defined(MIPS3)
nop # required for QED5230
nop # required for QED5230
@@ -1806,8 +1864,8 @@ LEAF(MIPSX(tlb_update))
tlbwi # update slot found
COP0_SYNC
#ifdef MIPS3_LOONGSON2
- li k0, MIPS_DIAG_ITLB_CLEAR
- mtc0 v0, MIPS_COP_0_DIAG # invalidate ITLB
+ li t1, MIPS_DIAG_ITLB_CLEAR
+ mtc0 t1, MIPS_COP_0_DIAG # invalidate ITLB
#elif defined(MIPS3)
nop # required for QED5230
nop # required for QED5230
@@ -1927,7 +1985,7 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_addr
tlbwi
COP0_SYNC
#ifdef MIPS3_LOONGSON2
- li k0, MIPS_DIAG_ITLB_CLEAR
+ li v0, MIPS_DIAG_ITLB_CLEAR
mtc0 v0, MIPS_COP_0_DIAG # invalidate ITLB
#elif defined(MIPS3)
nop
@@ -1997,7 +2055,7 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_asid
COP0_SYNC
#ifdef MIPS3_LOONGSON2
- li k0, MIPS_DIAG_ITLB_CLEAR
+ li v0, MIPS_DIAG_ITLB_CLEAR
mtc0 v0, MIPS_COP_0_DIAG # invalidate ITLB
#endif
@@ -2052,7 +2110,7 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_glob
COP0_SYNC
#ifdef MIPS3_LOONGSON2
- li k0, MIPS_DIAG_ITLB_CLEAR
+ li v0, MIPS_DIAG_ITLB_CLEAR
mtc0 v0, MIPS_COP_0_DIAG # invalidate ITLB
#endif
@@ -2100,7 +2158,7 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_all)
COP0_SYNC
#ifdef MIPS3_LOONGSON2
- li k0, MIPS_DIAG_ITLB_CLEAR
+ li v0, MIPS_DIAG_ITLB_CLEAR
mtc0 v0, MIPS_COP_0_DIAG # invalidate ITLB
#endif
@@ -2261,14 +2319,12 @@ LEAF(MIPSX(tlb_enter))
COP0_SYNC
_MTC0 ta1, MIPS_COP_0_TLB_HI # restore EntryHi
-
#ifdef MIPS3_LOONGSON2
- li k0, MIPS_DIAG_ITLB_CLEAR
+ li v0, MIPS_DIAG_ITLB_CLEAR
mtc0 v0, MIPS_COP_0_DIAG # invalidate ITLB
#endif
-
- JR_HB_RA
.set at
+ JR_HB_RA
END(MIPSX(tlb_enter))
/*
@@ -2502,7 +2558,7 @@ LEAF(MIPSX(tlb_write_indexed))
COP0_SYNC
#ifdef MIPS3_LOONGSON2
- li k0, MIPS_DIAG_ITLB_CLEAR
+ li v0, MIPS_DIAG_ITLB_CLEAR
mtc0 v0, MIPS_COP_0_DIAG # invalidate ITLB
#endif
@@ -2539,12 +2595,12 @@ LEAF_NOPROFILE(MIPSX(VCED))
cache (CACHE_R4K_D | CACHEOP_R4K_HIT_INV), 0(k0)
#ifdef DEBUG
_MFC0 k0, MIPS_COP_0_BAD_VADDR
- PTR_LA k1, VCED_vaddr
+ PTR_LA k1, MIPSX(VCED_vaddr)
PTR_S k0, 0(k1)
_MFC0 k0, MIPS_COP_0_EXC_PC
- PTR_LA k1, VCED_epc
+ PTR_LA k1, MIPSX(VCED_epc)
PTR_S k0, 0(k1)
- PTR_LA k1, VCED_count # count number of exceptions
+ PTR_LA k1, MIPSX(VCED_count) # count number of exceptions
PTR_SRL k0, k0, 26 # position upper 4 bits of VA
and k0, k0, 0x3c # mask it off
PTR_ADDU k1, k0 # get address of count table
@@ -2557,14 +2613,14 @@ LEAF_NOPROFILE(MIPSX(VCED))
#ifdef DEBUG
.data
- .globl _C_LABEL(VCED_count)
-_C_LABEL(VCED_count):
+ .globl _C_LABEL(MIPSX(VCED_count))
+_C_LABEL(MIPSX(VCED_count)):
LONG_WORD 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
- .globl _C_LABEL(VCED_epc)
-_C_LABEL(VCED_epc):
+ .globl _C_LABEL(MIPSX(VCED_epc))
+_C_LABEL(MIPSX(VCED_epc)):
PTR_WORD 0
- .globl _C_LABEL(VCED_vaddr)
-_C_LABEL(VCED_vaddr):
+ .globl _C_LABEL(MIPSX(VCED_vaddr))
+_C_LABEL(MIPSX(VCED_vaddr)):
PTR_WORD 0
.text
#endif
@@ -2577,9 +2633,9 @@ LEAF_NOPROFILE(MIPSX(VCEI))
cache (CACHE_R4K_I | CACHEOP_R4K_HIT_INV), 0(k0)
#ifdef DEBUG
_MFC0 k0, MIPS_COP_0_BAD_VADDR
- PTR_LA k1, VCEI_vaddr
+ PTR_LA k1, MIPSX(VCEI_vaddr)
PTR_S k0, 0(k1)
- PTR_LA k1, VCEI_count # count number of exceptions
+ PTR_LA k1, MIPSX(VCEI_count) # count number of exceptions
PTR_SRL k0, k0, 26 # position upper 4 bits of VA
and k0, k0, 0x3c # mask it off
PTR_ADDU k1, k0 # get address of count table
@@ -2592,11 +2648,11 @@ LEAF_NOPROFILE(MIPSX(VCEI))
#ifdef DEBUG
.data
- .globl _C_LABEL(VCEI_count)
-_C_LABEL(VCEI_count):
+ .globl _C_LABEL(MIPSX(VCEI_count))
+_C_LABEL(MIPSX(VCEI_count)):
LONG_WORD 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
- .globl _C_LABEL(VCEI_vaddr)
-_C_LABEL(VCEI_vaddr):
+ .globl _C_LABEL(MIPSX(VCEI_vaddr))
+_C_LABEL(MIPSX(VCEI_vaddr)):
PTR_WORD 0
.text
#endif
@@ -2740,3 +2796,7 @@ MIPSX(excpt_sw):
#else
PTR_WORD _C_LABEL(MIPSX(user_gen_exception)) # 31
#endif
+#ifdef MIPS3_LOONGSON2
+loongson2_xtlb_miss_str:
+ .string "loongson2_xtlb_miss"
+#endif
Index: mips/mips_fixup.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/mips_fixup.c,v
retrieving revision 1.7
diff -u -p -u -r1.7 mips_fixup.c
--- mips/mips_fixup.c 17 Aug 2011 14:39:59 -0000 1.7
+++ mips/mips_fixup.c 24 Aug 2011 17:21:23 -0000
@@ -239,7 +239,7 @@ mips_fixup_addr(const uint32_t *stubp)
* jr t9
* nop
*
- * Or for loongson2:
+ * Or for loongson2 (
* lui v0, %hi(sym)
* lX t9, %lo(sym)(v0)
* lui at,0xcfff
@@ -247,9 +247,16 @@ mips_fixup_addr(const uint32_t *stubp)
* and t9,t9,at
* jr t9
* move at,at
+ * or:
+ * lui v0, %hi(sym)
+ * lX t9, %lo(sym)(v0)
+ * li at, 0x3
+ * dmtc0 at, $22
+ * jr t9
+ * nop
*/
mips_reg_t regs[32];
- uint32_t used = 0;
+ uint32_t used = 1;
size_t n;
const char *errstr = "mips";
/*
@@ -280,7 +287,7 @@ mips_fixup_addr(const uint32_t *stubp)
goto out;
}
regs[insn.IType.rt] = *(const int32_t *)
- (regs[insn.IType.rs] + (int16_t)insn.IType.imm);
+ ((vaddr_t)regs[insn.IType.rs] +
(int16_t)insn.IType.imm);
used |= (1 << insn.IType.rt);
break;
#endif
@@ -292,6 +299,23 @@ mips_fixup_addr(const uint32_t *stubp)
regs[insn.IType.rt] |= insn.IType.imm;
used |= (1 << insn.IType.rt);
break;
+ case OP_COP0:
+ switch (insn.RType.rs) {
+ case OP_DMT:
+ if (insn.RType.rd != 22) {
+ errstr = "dmtc0 dst";
+ goto out;
+ }
+ if ((used & (1 << insn.RType.rt)) == 0) {
+ errstr = "dmtc0 src";
+ goto out;
+ }
+ break;
+ default:
+ errstr = "COP0";
+ goto out;
+ }
+ break;
case OP_SPECIAL:
switch (insn.RType.func) {
case OP_JR:
Index: bonito/bonito_pci.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/bonito/bonito_pci.c,v
retrieving revision 1.9
diff -u -p -u -r1.9 bonito_pci.c
--- bonito/bonito_pci.c 10 Jul 2011 23:13:22 -0000 1.9
+++ bonito/bonito_pci.c 24 Aug 2011 17:21:23 -0000
@@ -66,11 +66,14 @@ pcireg_t bonito_conf_read(void *, pcitag
void bonito_conf_write(void *, pcitag_t, int, pcireg_t);
void
-bonito_pci_init(pci_chipset_tag_t pc, struct bonito_config *bc)
+bonito_pci_init(pci_chipset_tag_t pc, const struct bonito_config *bc)
{
- pc->pc_conf_v = bc;
- pc->pc_attach_hook = bonito_attach_hook;
+ pc->pc_conf_v = __UNCONST(bc);
+ if (bc->bc_attach_hook != NULL)
+ pc->pc_attach_hook = bc->bc_attach_hook;
+ else
+ pc->pc_attach_hook = bonito_attach_hook;
pc->pc_bus_maxdevs = bonito_bus_maxdevs;
pc->pc_make_tag = bonito_make_tag;
pc->pc_decompose_tag = bonito_decompose_tag;
Index: bonito/bonitoreg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/bonito/bonitoreg.h,v
retrieving revision 1.6
diff -u -p -u -r1.6 bonitoreg.h
--- bonito/bonitoreg.h 24 Dec 2005 20:07:19 -0000 1.6
+++ bonito/bonitoreg.h 24 Aug 2011 17:21:23 -0000
@@ -22,7 +22,14 @@
#define BONITO(x) (BONITO_REG_BASE + (x))
+
+#ifdef _LP64
+#define REGVAL(x) *((volatile u_int32_t
*)MIPS_PHYS_TO_XKPHYS_UNCACHED(x))
+#define REGVAL8(x) *((volatile u_int8_t
*)MIPS_PHYS_TO_XKPHYS_UNCACHED(x))
+#else
#define REGVAL(x) *((volatile u_int32_t *) MIPS_PHYS_TO_KSEG1(x))
+#define REGVAL8(x) *((volatile u_int8_t *)MIPS_PHYS_TO_KSEG1(x))
+#endif
#define BONITO_BOOT_BASE 0x1fc00000
#define BONITO_BOOT_SIZE 0x00100000
@@ -48,7 +55,11 @@
#define BONITO_PCIHI_BASE 0x20000000
#define BONITO_PCIHI_SIZE 0x20000000
#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
+#define LS2F_PCIHI_BASE 0x40000000UL
+#define LS2F_PCIHI_SIZE 0x40000000UL
+#define LS2F_PCIHI_TOP (LS2F_PCIHI_BASE+LS2F_PCIHI_SIZE-1)
#define BONITO_PCIIO_BASE 0x1fd00000
+#define BONITO_PCIIO_LEGACY 0x00004000UL
#define BONITO_PCIIO_SIZE 0x00100000
#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
#define BONITO_PCICFG_BASE 0x1fe80000
@@ -409,4 +420,105 @@
#define BONITO_TIMERCFG BONITO(BONITO_REGBASE + 0x60)
+
+/*
+ * Bonito interrupt assignments
+ */
+
+/*
+ * Loongson 2F assignments
+ */
+
+#define LOONGSON_INTR_GPIO0 0
+#define LOONGSON_INTR_GPIO1 1
+#define LOONGSON_INTR_GPIO2 2
+#define LOONGSON_INTR_GPIO3 3
+
+/* pci interrupts */
+#define LOONGSON_INTR_PCIA 4
+#define LOONGSON_INTR_PCIB 5
+#define LOONGSON_INTR_PCIC 6
+#define LOONGSON_INTR_PCID 7
+
+#define LOONGSON_INTR_PCI_PARERR 8
+#define LOONGSON_INTR_PCI_SYSERR 9
+#define LOONGSON_INTR_DRAM_PARERR 10
+
+/* non-PCI interrupts */
+#define LOONGSON_INTR_INT0 11
+#define LOONGSON_INTR_INT1 12
+#define LOONGSON_INTR_INT2 13
+#define LOONGSON_INTR_INT3 14
+
+#define LOONGSON_INTRMASK_GPIO0 0x00000001 /* can't
interrupt */
+#define LOONGSON_INTRMASK_GPIO1 0x00000002
+#define LOONGSON_INTRMASK_GPIO2 0x00000004
+#define LOONGSON_INTRMASK_GPIO3 0x00000008
+
+#define LOONGSON_INTRMASK_GPIO 0x0000000f
+
+/* pci interrupts */
+#define LOONGSON_INTRMASK_PCIA 0x00000010
+#define LOONGSON_INTRMASK_PCIB 0x00000020
+#define LOONGSON_INTRMASK_PCIC 0x00000040
+#define LOONGSON_INTRMASK_PCID 0x00000080
+
+#define LOONGSON_INTRMASK_PCI_PARERR 0x00000100
+#define LOONGSON_INTRMASK_PCI_SYSERR 0x00000200
+#define LOONGSON_INTRMASK_DRAM_PARERR 0x00000400
+
+/* non-PCI interrupts */
+#define LOONGSON_INTRMASK_INT0 0x00000800
+#define LOONGSON_INTRMASK_INT1 0x00001000
+#define LOONGSON_INTRMASK_INT2 0x00002000
+#define LOONGSON_INTRMASK_INT3 0x00004000
+
+#define LOONGSON_INTRMASK_LVL0 0x00007800 /* not maskable in
bonito */
+#define LOONGSON_INTRMASK_LVL4 0x000007ff
+
+/*
+ * Loongson 2E (Bonito64) assignments
+ */
+
+#define BONITO_INTRMASK_MBOX 0x0000000f
+#define BONITO_INTR_MBOX 0
+#define BONITO_INTRMASK_DMARDY 0x00000010
+#define BONITO_INTRMASK_DMAEMPTY 0x00000020
+#define BONITO_INTRMASK_COPYRDY 0x00000040
+#define BONITO_INTRMASK_COPYEMPTY 0x00000080
+#define BONITO_INTRMASK_COPYERR 0x00000100
+#define BONITO_INTRMASK_PCIIRQ 0x00000200
+#define BONITO_INTRMASK_MASTERERR 0x00000400
+#define BONITO_INTRMASK_SYSTEMERR 0x00000800
+#define BONITO_INTRMASK_DRAMPERR 0x00001000
+#define BONITO_INTRMASK_RETRYERR 0x00002000
+#define BONITO_INTRMASK_GPIO 0x01ff0000
+#define BONITO_INTR_GPIO 16
+#define BONITO_INTRMASK_GPIN 0x7e000000
+#define BONITO_INTR_GPIN 25
+
+/*
+ * Bonito interrupt handling recipes:
+ * - we have up to 32 interrupts at the Bonito level.
+ * - systems with ISA devices also have 16 (well, 15) ISA interrupts with the
+ * usual 8259 pair. Bonito and ISA interrupts happen on two different levels.
+ *
+ * These arbitrary values may be changed as long as interrupt mask variables
+ * use large enough integer types and always use the following macros to
+ * handle interrupt masks.
+ */
+
+#define INTPRI_BONITO (INTPRI_CLOCK + 1)
+#define INTPRI_ISA (INTPRI_BONITO + 1)
+
+#define BONITO_NDIRECT 32
+#define BONITO_NISA 16
+#define BONITO_NINTS (BONITO_NDIRECT + BONITO_NISA)
+#define BONITO_ISA_IRQ(i) ((i) + BONITO_NDIRECT)
+#define BONITO_DIRECT_IRQ(i) (i)
+#define BONITO_IRQ_IS_ISA(i) ((i) >= BONITO_NDIRECT)
+#define BONITO_IRQ_TO_ISA(i) ((i) - BONITO_NDIRECT)
+
+#define BONITO_DIRECT_MASK(imask) ((imask) & ((1L <<
BONITO_NDIRECT) - 1))
+#define BONITO_ISA_MASK(imask) ((imask) >> BONITO_NDIRECT)
#endif /* _BONITO_H_ */
Index: bonito/bonitovar.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/bonito/bonitovar.h,v
retrieving revision 1.4
diff -u -p -u -r1.4 bonitovar.h
--- bonito/bonitovar.h 28 Apr 2008 20:23:28 -0000 1.4
+++ bonito/bonitovar.h 24 Aug 2011 17:21:23 -0000
@@ -42,10 +42,15 @@ struct bonito_config {
uint32_t bc_intEdge;
uint32_t bc_intSteer;
uint32_t bc_intPol;
+
+ /* PCI Attach hook , if needed */
+ void (*bc_attach_hook)(device_t, device_t,
+ struct pcibus_attach_args *);
+
};
#ifdef _KERNEL
-void bonito_pci_init(pci_chipset_tag_t, struct bonito_config *);
+void bonito_pci_init(pci_chipset_tag_t, const struct bonito_config *);
void bonito_iobc_wbinv_range(paddr_t, psize_t);
void bonito_iobc_inv_range(paddr_t, psize_t);
Index: lib/libc/arch/mips/atomic/atomic_add.S
===================================================================
RCS file: /cvsroot/src/common/lib/libc/arch/mips/atomic/atomic_add.S,v
retrieving revision 1.2
diff -u -p -u -r1.2 atomic_add.S
--- lib/libc/arch/mips/atomic/atomic_add.S 14 Dec 2009 00:38:59 -0000
1.2
+++ lib/libc/arch/mips/atomic/atomic_add.S 24 Aug 2011 17:21:52 -0000
@@ -33,9 +33,18 @@
RCSID("$NetBSD: atomic_add.S,v 1.2 2009/12/14 00:38:59 matt Exp $")
.text
- .set noat
.set noreorder
+#ifdef _KERNEL_OPT
+#include "opt_cputype.h"
+#ifndef MIPS3_LOONGSON2F
+ .set noat
+ .set nomacro
+#endif
+#else /* _KERNEL_OPT */
+ .set noat
.set nomacro
+#endif /* _KERNEL_OPT */
+
LEAF(_atomic_add_32)
1: INT_LL t0, 0(a0)
Index: lib/libc/arch/mips/atomic/atomic_and.S
===================================================================
RCS file: /cvsroot/src/common/lib/libc/arch/mips/atomic/atomic_and.S,v
retrieving revision 1.2
diff -u -p -u -r1.2 atomic_and.S
--- lib/libc/arch/mips/atomic/atomic_and.S 14 Dec 2009 00:38:59 -0000
1.2
+++ lib/libc/arch/mips/atomic/atomic_and.S 24 Aug 2011 17:21:52 -0000
@@ -33,9 +33,18 @@
RCSID("$NetBSD: atomic_and.S,v 1.2 2009/12/14 00:38:59 matt Exp $")
.text
- .set noat
.set noreorder
+#ifdef _KERNEL_OPT
+#include "opt_cputype.h"
+#ifndef MIPS3_LOONGSON2F
+ .set noat
+ .set nomacro
+#endif
+#else /* _KERNEL_OPT */
+ .set noat
.set nomacro
+#endif /* _KERNEL_OPT */
+
LEAF(_atomic_and_32)
1: INT_LL t0, 0(a0)
Index: lib/libc/arch/mips/atomic/atomic_dec.S
===================================================================
RCS file: /cvsroot/src/common/lib/libc/arch/mips/atomic/atomic_dec.S,v
retrieving revision 1.2
diff -u -p -u -r1.2 atomic_dec.S
--- lib/libc/arch/mips/atomic/atomic_dec.S 14 Dec 2009 00:39:00 -0000
1.2
+++ lib/libc/arch/mips/atomic/atomic_dec.S 24 Aug 2011 17:21:52 -0000
@@ -33,9 +33,17 @@
RCSID("$NetBSD: atomic_dec.S,v 1.2 2009/12/14 00:39:00 matt Exp $")
.text
- .set noat
.set noreorder
+#ifdef _KERNEL_OPT
+#include "opt_cputype.h"
+#ifndef MIPS3_LOONGSON2F
+ .set noat
+ .set nomacro
+#endif
+#else /* _KERNEL_OPT */
+ .set noat
.set nomacro
+#endif /* _KERNEL_OPT */
LEAF(_atomic_dec_32)
1: INT_LL t0, 0(a0)
Index: lib/libc/arch/mips/atomic/atomic_inc.S
===================================================================
RCS file: /cvsroot/src/common/lib/libc/arch/mips/atomic/atomic_inc.S,v
retrieving revision 1.2
diff -u -p -u -r1.2 atomic_inc.S
--- lib/libc/arch/mips/atomic/atomic_inc.S 14 Dec 2009 00:39:00 -0000
1.2
+++ lib/libc/arch/mips/atomic/atomic_inc.S 24 Aug 2011 17:21:52 -0000
@@ -33,9 +33,18 @@
RCSID("$NetBSD: atomic_inc.S,v 1.2 2009/12/14 00:39:00 matt Exp $")
.text
- .set noat
.set noreorder
+#ifdef _KERNEL_OPT
+#include "opt_cputype.h"
+#ifndef MIPS3_LOONGSON2F
+ .set noat
+ .set nomacro
+#endif
+#else /* _KERNEL_OPT */
+ .set noat
.set nomacro
+#endif /* _KERNEL_OPT */
+
LEAF(_atomic_inc_32)
1: INT_LL t0, 0(a0)
Index: lib/libc/arch/mips/atomic/atomic_or.S
===================================================================
RCS file: /cvsroot/src/common/lib/libc/arch/mips/atomic/atomic_or.S,v
retrieving revision 1.2
diff -u -p -u -r1.2 atomic_or.S
--- lib/libc/arch/mips/atomic/atomic_or.S 14 Dec 2009 00:39:00 -0000
1.2
+++ lib/libc/arch/mips/atomic/atomic_or.S 24 Aug 2011 17:21:52 -0000
@@ -31,9 +31,17 @@
#include "atomic_op_asm.h"
.text
- .set noat
.set noreorder
+#ifdef _KERNEL_OPT
+#include "opt_cputype.h"
+#ifndef MIPS3_LOONGSON2F
+ .set noat
+ .set nomacro
+#endif
+#else /* _KERNEL_OPT */
+ .set noat
.set nomacro
+#endif /* _KERNEL_OPT */
LEAF(_atomic_or_32)
1: INT_LL t0, 0(a0)
Index: lib/libc/arch/mips/atomic/atomic_swap.S
===================================================================
RCS file: /cvsroot/src/common/lib/libc/arch/mips/atomic/atomic_swap.S,v
retrieving revision 1.2
diff -u -p -u -r1.2 atomic_swap.S
--- lib/libc/arch/mips/atomic/atomic_swap.S 14 Dec 2009 00:39:00 -0000
1.2
+++ lib/libc/arch/mips/atomic/atomic_swap.S 24 Aug 2011 17:21:52 -0000
@@ -33,9 +33,18 @@
RCSID("$NetBSD: atomic_swap.S,v 1.2 2009/12/14 00:39:00 matt Exp $")
.text
- .set noat
.set noreorder
+#ifdef _KERNEL_OPT
+#include "opt_cputype.h"
+#ifndef MIPS3_LOONGSON2F
+ .set noat
+ .set nomacro
+#endif
+#else /* _KERNEL_OPT */
+ .set noat
.set nomacro
+#endif /* _KERNEL_OPT */
+
LEAF(_atomic_swap_32)
1: INT_LL v0, 0(a0)
Index: lib/libc/arch/mips/string/bcopy.S
===================================================================
RCS file: /cvsroot/src/common/lib/libc/arch/mips/string/bcopy.S,v
retrieving revision 1.3
diff -u -p -u -r1.3 bcopy.S
--- lib/libc/arch/mips/string/bcopy.S 14 Dec 2009 00:39:00 -0000 1.3
+++ lib/libc/arch/mips/string/bcopy.S 24 Aug 2011 17:21:53 -0000
@@ -170,8 +170,10 @@ LEAF(FUNCTION)
PTR_ADDU DSTREG,1
4: # copydone
+ .set at #-mfix-loongson2f-btb
j ra
nop
+ .set noat
/*
* Copy from unaligned source to aligned dest.
@@ -264,8 +266,10 @@ LEAF(FUNCTION)
PTR_SUBU DSTREG,1
4: # copydone
+ .set at #-mfix-loongson2f-btb
j ra
nop
+ .set noat
/*
* Copy from unaligned source to aligned dest.
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