Re: standard runtime for (possible/hopeful) 64bit kernels

[Simon Burge <simonb%NetBSD.org@localhost>]

"Toru Nishimura" wrote:

> > no 64-bit CPUs that only implement the old R3K style 32 x 32-bit
> > FPU.
> > 
> > That said, there's some MIPS32 CPUs with a "64-bit" FPU that have the
> > full 32 64-bit FP regs, but that's a different answer to a question you
> > didn't ask :-)
> 
> Um, just out of curiousities, how 64bit FP math load/store is implemented
> in that case?  In orginal MIPS design FP circuit was physically
> independent piece of HW from main ALU unit, and special insn encoding
> space was assigned.  Beginning from? R4300i, integer circuit started
> snacking FP unit and GP can optionally used for FP arith, partly because
> MUL/DIV by FP circuit was faster than standard MULhi/MULlo function
> block.  It seems e500 core follows the similar rationle.

I don't recall the details, but the 74Kf was the MIPS32 CPU I know of
that has an FPU.  A quick look at the data sheet says it has a single
load/store unit, and that CP1 loads/stores are sent via that single
load/store unit, so I'm not sure if FP reg loads are broken into 32-bit
chunks or not...

Cheers,
Simon.