Re: MP(G2)

["Naruaki.Etomi" <nullnilaki%gmail.com@localhost>]

Dear Michael-san

It's been a long time.
Thank you for your interest.

I'll answer your questions, though my answers may be poor...

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-----------------------------------------------------------------------------
The following processing is required within the md_setup_trampoline() function.
#endif /* OPENPIC */
/* Start secondary CPU and stop timebase. */
out32(0xf2800000, (int)cpu_spinup_trampoline);
cpu_send_ipi(1, IPI_NOMESG);
#ifdef OPENPIC

The following processing is required within the md_presync_timebase() function.
{
/* sync timebase (XXX shouldn't be zero'ed) */
__asm volatile ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0));
}

The following processing is required within the md_start_timebase() function.
/*
* wait for secondary spin up (1.5ms @ 604/200MHz)
* XXX we cannot use delay() here because timebase is not
* running.
*/
for (i = 0; i < 100000; i++)
if (h->hatch_running)
break;

/* Start timebase. */
out32(0xf2800000, 0x100);
cpu_send_ipi(1, IPI_NOMESG);

The following processing is required within the md_setup_interrupts() function.
#endif /* OPENPIC */
out32(HH_INTR_SECONDARY, ~0); /* Reset interrupt. */
}
-----------------------------------------------------------------------------

The above process is necessary for G2 CPU initialization.
However, it will not compile for the following reasons.

===========================================================
1 #ifndef OPENPIC
  ┗ OK
2 #if NPIC_OPENPIC > 0
  ┗ #include "opt_interrupt.h" = Always becomes 1
3 #define OPENPIC
  ┗  I am in trouble...
===========================================================

> Why do you need this part?
>
> > diff -Naru src.orig/sys/arch/macppc/macppc/cpu.c
> > src/sys/arch/macppc/macppc/cpu.c
> > --- src.orig/sys/arch/macppc/macppc/cpu.c 2023-08-03
> > 08:16:31.000000000 +0000 +++ src/sys/arch/macppc/macppc/cpu.c
> > 2026-04-12 00:58:12.958727695 +0000 @@ -70,12 +70,15 @@
> >
> >  #include "pic_openpic.h"
> >  #include "pic_u3_ht.h"
> > +#include "pic_ohare.h"
> >
> > +#ifndef NPIC_OHARE
> >  #ifndef OPENPIC
> >  #if NPIC_OPENPIC > 0
> >  #define OPENPIC
> >  #endif /* NOPENPIC > 0 */
> >  #endif /* OPENPIC */
> > +#endif /* NOOHARE */
> >
> >  int cpumatch(device_t, cfdata_t, void *);
> >  void cpuattach(device_t, device_t, void *);
>
> ... I left it out and both GENERIC.MP and and my other openpic-only SMP
> kernels build just fine.

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

★As far as I could find, the most detailed explanation of G2 IPI was
in the following document.
https://cs.iossec.tech/xnu/xnu-201/source/osfmk/ppc/POWERMAC/mp/MP_2p.s#L209
https://cs.iossec.tech/xnu/xnu-201/source/osfmk/ppc/POWERMAC/mp/MP_2p.s#L1348

★Please pay attention
https://cs.iossec.tech/xnu/xnu-201/source/osfmk/ppc/POWERMAC/mp/MP_2p.s#L1367

IPI is generated by an external interrupt.
It says that MACE malfunctions because of Secondary to primary interrupt,
but according to the following, it will probably be fine.
(mc0 at obio0 offset 0x11000: irq 14,2,3)

-----------------------------------------------------------------------------
struct powermac_interrupt  powermac_pci_interrupts[NPCI_INTERRUPTS] = {
{ 0, 0, PMAC_DEV_CARD4},   /* Bit 24 - External Int 4 */
{ 0, 0, PMAC_DEV_CARD5},   /* Bit 25 - External Int 5 */
{ 0, 0, PMAC_DEV_CARD6},   /* Bit 26 - External Int 6 */
{ 0, 0, PMAC_DEV_CARD7},   /* Bit 27 - External Int 7 */
{ 0, 0, PMAC_DEV_CARD8},   /* Bit 28 - External Int 8 */
{ 0, 0, PMAC_DEV_CARD9},   /* Bit 29 - External Int 9 */
{ 0, 0, PMAC_DEV_CARD10},   /* Bit 30 - External Int 10 */
{ 0, 0, -1},   /* Bit 31 - Reserved */
{ 0, 0, PMAC_DEV_SCC_B},   /* Bit 16 - SCC Channel B */
{ 0, 0, PMAC_DEV_AUDIO},   /* Bit 17 - Audio */
{ pci_via1_interrupt,SPLTTY,-1},  /* Bit 18 - VIA (cuda/pmu) */
{ 0, 0, PMAC_DEV_FLOPPY},   /* Bit 19 - SwimIII/Floppy */
{ 0, 0, PMAC_DEV_CARD0},   /* Bit 20 - External Int 0 */
{ 0, 0, PMAC_DEV_CARD1},   /* Bit 21 - External Int 1 */
{ 0, 0, PMAC_DEV_CARD2},   /* Bit 22 - External Int 2 */
{ 0, 0, PMAC_DEV_CARD3},   /* Bit 23 - External Int 3 */
{ 0, 0, PMAC_DMA_AUDIO_OUT},   /* Bit 8 - DMA Audio Out */
{ 0, 0, PMAC_DMA_AUDIO_IN},   /* Bit 9 - DMA Audio In */
{ 0, 0, PMAC_DMA_SCSI1},   /* Bit 10 - DMA SCSI 1 */
{ 0, 0, PMAC_DEV_NMI},   /* Bit 11 - Reserved */
{ 0, 0, PMAC_DEV_SCSI0},   /* Bit 12 - SCSI 0 */
{ 0, 0, PMAC_DEV_SCSI1},   /* Bit 13 - SCSI 1 */
{ 0, 0, PMAC_DEV_ETHERNET},   /* Bit 14 - MACE/Ethernet */
{ 0, 0, PMAC_DEV_SCC_A},   /* Bit 15 - SCC Channel A */
{ 0, 0, PMAC_DMA_SCSI0},   /* Bit 0 - DMA SCSI 0 */
{ 0, 0, PMAC_DMA_FLOPPY},   /* Bit 1 - DMA Floppy */
{ 0, 0, PMAC_DMA_ETHERNET_TX}, /* Bit 2 - DMA Ethernet Tx */
{ 0, 0, PMAC_DMA_ETHERNET_RX}, /* Bit 3 - DMA Ethernet Rx */
{ 0, 0, PMAC_DMA_SCC_A_TX},   /* Bit 4 - DMA SCC Channel A TX */
{ 0, 0, PMAC_DMA_SCC_A_RX},   /* Bit 5 - DMA SCC Channel A RX */
{ 0, 0, PMAC_DMA_SCC_B_TX},   /* Bit 6 - DMA SCC Channel B TX */
{ 0, 0, PMAC_DMA_SCC_B_RX}   /* Bit 7 - DMA SCC Channel B RX */
};
-----------------------------------------------------------------------------

I implemented the following process to prevent interrupts from being masked.
(0x40000000 == 1 << GC_IPI_IRQ)

-----------------------------------------------------------------------------
+
+#ifdef MULTIPROCESSOR
+ ohare->enable_mask = 0x40000000;
+#else
  ohare->enable_mask = 0;
+#endif /*MULTIPROCESSOR*/
+
-----------------------------------------------------------------------------

As far as I've researched, hh_establish_ipi function cannot be enabled.
The following also works.

-----------------------------------------------------------------------------
hh_establish_ipi(int type, int level, void *ih_args)
{
#if 0
intr_establish_xname(ipiops.ppc_ipi_vector, type, level, ipi_intr,
    ih_args, "hh ipi");
#endif
}
-----------------------------------------------------------------------------

> Finally, we register an IPI handler in ipi_hammerhead.c - why not use a
> custom handler that deals with the GPIO writes, calls ipi_intr(), and
> leave pic_ohare.c alone? That way we wouldn't need special treatment
> for IPIs and all the support code would be in ipi_hammerhead.c

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

I apologize if I've said anything incorrect...
Thanks,
-- 
Naruaki Etomi
nullnilaki%gmail.com@localhost