MP(G2)

["Naruaki.Etomi" <nullnilaki%gmail.com@localhost>]

Hello!

It's been a while since I reported NetBSD PR #57394, but I've managed
to get the second CPU working again on my G2 macppc.
(It still just runs and generates heat, though.)
https://dmesgd.nycbug.org/dmesgd?do=view&id=8907

I'm thinking of using DayStar CPU cards, like those used in the
9500/180MP and 9600/200MP.
UMAX MP configurations don't work.

Daystar 4CPU cards also don't work.
I have the 【Daystar frame】, but I threw it away a long time ago
because I didn't understand the value of the CPU.
Would anyone be willing to sell me one? ;-)
https://x.com/nullnilaki/status/2028223469012615276

I'm hobbyist/amateur programmer, so the source code is messy, but I'll
leave a patch here.
(NetBSD 11.0_RC2 version)

I'll submit a pull request for the Current version once it works a bit better.

---------------------------------------------------------------------------------------------------

Regarding the following design flaws
┗ macppc/cpu.c contains OpenPIC machine's CPU setup code and Grand
Central machine's CPU setup code.
    However, the Grand Central side of the code cannot be compiled.
    My patch fails to compile on the OpenPIC side.
    How can I fix it neatly?

diff -Naru src.orig/sys/arch/macppc/macppc/cpu.c
src/sys/arch/macppc/macppc/cpu.c
--- src.orig/sys/arch/macppc/macppc/cpu.c 2023-08-03 08:16:31.000000000 +0000
+++ src/sys/arch/macppc/macppc/cpu.c 2026-04-12 00:58:12.958727695 +0000
@@ -70,12 +70,15 @@

 #include "pic_openpic.h"
 #include "pic_u3_ht.h"
+#include "pic_ohare.h"

+#ifndef NPIC_OHARE
 #ifndef OPENPIC
 #if NPIC_OPENPIC > 0
 #define OPENPIC
 #endif /* NOPENPIC > 0 */
 #endif /* OPENPIC */
+#endif /* NOOHARE */

 int cpumatch(device_t, cfdata_t, void *);
 void cpuattach(device_t, device_t, void *);

---------------------------------------------------------------------------------------------------
diff -Naru src.orig/sys/arch/macppc/macppc/ipi_hammerhead.c
src/sys/arch/macppc/macppc/ipi_hammerhead.c
--- src.orig/sys/arch/macppc/macppc/ipi_hammerhead.c 2023-12-20
15:29:05.000000000 +0000
+++ src/sys/arch/macppc/macppc/ipi_hammerhead.c 2026-04-19
09:14:28.937710165 +0000
@@ -50,6 +50,7 @@
 #define HH_INTR_SECONDARY 0xf80000c0
 #define HH_INTR_PRIMARY 0xf3019000
 #define GC_IPI_IRQ 30
+#define INT_CLEAR_REG     0xf3000028

 void
 setup_hammerhead_ipi(void)
@@ -63,10 +64,12 @@
 hh_send_ipi(cpuid_t target, uint32_t mesg)
 {
  int cpu_id = target;
+ uint32_t ipimask = 1 << GC_IPI_IRQ;

  if (target == IPI_DST_ALL) {
  atomic_or_32(&cpu_info[0].ci_pending_ipis, mesg);
  atomic_or_32(&cpu_info[1].ci_pending_ipis, mesg);
+ out32rb(INT_CLEAR_REG, ipimask);
  in32(HH_INTR_PRIMARY);
  out32(HH_INTR_SECONDARY, ~0);
  out32(HH_INTR_SECONDARY, 0);
@@ -80,6 +83,7 @@
  atomic_or_32(&cpu_info[cpu_id].ci_pending_ipis, mesg);
  switch (cpu_id) {
  case 0:
+ out32rb(INT_CLEAR_REG, ipimask);
  in32(HH_INTR_PRIMARY);
  break;
  case 1:
@@ -96,4 +100,4 @@
      ih_args, "hh ipi");
 }

-#endif /*MULTIPROCESSOR*/
+#endif /*MULTIPROCESSOR*/
\ No newline at end of file
diff -Naru src.orig/sys/arch/macppc/macppc/pic_ohare.c
src/sys/arch/macppc/macppc/pic_ohare.c
--- src.orig/sys/arch/macppc/macppc/pic_ohare.c 2021-03-05
07:15:53.000000000 +0000
+++ src/sys/arch/macppc/macppc/pic_ohare.c 2026-04-19 09:21:04.776906939 +0000
@@ -31,6 +31,8 @@

 #include "opt_interrupt.h"

+#include "opt_interrupt.h"
+
 #include <sys/param.h>
 #include <sys/kmem.h>
 #include <sys/kernel.h>
@@ -144,7 +146,13 @@
  ohare->irqs[i] = 0;
  pic_add(pic);
  ohare->pending_events = 0;
+
+#ifdef MULTIPROCESSOR
+ ohare->enable_mask = 0x40000000;
+#else
  ohare->enable_mask = 0;
+#endif /*MULTIPROCESSOR*/
+
  out32rb(INT_ENABLE_REG, 0);
  out32rb(INT_CLEAR_REG, 0xffffffff);
  return ohare;
@@ -161,12 +169,20 @@
      "ohara2");
 }

+#define GC_IPI_IRQ 30
+
 static void
 ohare_enable_irq(struct pic_ops *pic, int irq, int type)
 {
  struct ohare_ops *ohare = (struct ohare_ops *)pic;
  uint32_t mask = 1 << irq;

+#ifdef MULTIPROCESSOR
+ if (irq == GC_IPI_IRQ) {
+ return;
+ }
+#endif /*MULTIPROCESSOR*/
+
  ohare->enable_mask |= mask;
  out32rb(INT_ENABLE_REG, ohare->enable_mask);
 }
@@ -178,6 +194,12 @@
  uint32_t levels;
  uint32_t mask = 1 << irq;

+#ifdef MULTIPROCESSOR
+ if (irq == GC_IPI_IRQ) {
+ return;
+ }
+#endif /*MULTIPROCESSOR*/
+
  ohare->enable_mask |= mask;
  out32rb(INT_ENABLE_REG, ohare->enable_mask);
  levels = in32rb(INT_STATE_REG);
@@ -193,6 +215,12 @@
  struct ohare_ops *ohare = (struct ohare_ops *)pic;
  uint32_t mask = 1 << irq;

+#ifdef MULTIPROCESSOR
+ if (irq == GC_IPI_IRQ) {
+ return;
+ }
+#endif /*MULTIPROCESSOR*/
+
  ohare->enable_mask &= ~mask;
  out32rb(INT_ENABLE_REG, ohare->enable_mask);
 }
@@ -217,6 +245,9 @@
 #endif
 }

+#define HH_INTR_SECONDARY 0xf80000c0
+extern int ipi_intr(void *);
+
 static int
 ohare_get_irq(struct pic_ops *pic, int mode)
 {
@@ -228,6 +259,22 @@
  int bail = 0;
 #endif

+#ifdef MULTIPROCESSOR
+ if(cpu_number() != 0) {
+ out32(HH_INTR_SECONDARY, ~0);
+ ipi_intr(NULL);
+ return 255;
+ }
+
+ uint32_t ipimask = 1 << GC_IPI_IRQ;
+ volatile uint32_t irqs = in32rb(INT_STATE_REG);
+
+ if (irqs & ipimask) {
+ out32rb(INT_CLEAR_REG, ipimask);
+ ipi_intr(NULL);
+ }
+#endif /*MULTIPROCESSOR*/
+
  if (ohare->pending_events == 0)
  ohare_read_events(ohare);
---------------------------------------------------------------------------------------------------

When I tried to selfbuild, it froze at the "make depend" step.
Engaging in a fierce battle against Deadlock!


Thanks,
-- 
Naruaki Etomi
nullnilaki%gmail.com@localhost