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Re: zs serial and interrupt sensitivity
On 5/3/11 12:39 PM, David Riley wrote:
> Switching the interrupts to level sensitive seems to have fixed my problems.
> Can anyone think of a good reason this should be edge-sensitive?
As I understand the Zilog interrupt system, the interrupt acknowledge
cycle should always bring /INT high again at least for a while, so an
edge-triggered interrupt should work. On the other hand, if /INT is
asserted, that means there definitely is a pending interrupt that needs
servicing... so making it level triggered should be more robust. :)
I don't know how the z8530 is connected to the rest of the interrupt
system on a macppc system, though; this is just my understanding of the
z8530 itself. Glancing through the zs driver code I can't even tell if
it's doing hardware or software INTACKs.
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