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Re: x86 pcitag_t change proposal/patch
On Fri, Apr 26, 2013 at 09:44:23AM -0500, Jonathan A. Kollasch wrote:
> On Fri, Apr 26, 2013 at 11:16:22AM +0900, Masanobu SAITOH wrote:
> > Hi, Jonathan
> > (2012/12/05 11:59), Jonathan A. Kollasch wrote:
> > >
> > >I'd like feedback on the attached patch.
> > >
> > >Commit message would be approximately as follows:
> > >
> > >Separate the implementation of PCI Configuration Access Mode 1 and
> > >Mode 2 from the x86 pcitag_t. This is desirable so that any tags
> > >possibly created prior to parsing of the ACPI MCFG table(s) can be
> > >used with a memory-mapped configuration space mechanism afterwards.
> > >
> > > Jonathan Kollasch
> > >
> > What's the current status of this work? I'd like to access to the PCIe
> > extended configuration space (from 0x100 to 0xfff) for debugging purpose.
> > There are a lot of important informations in it...
> I've been sitting on a revised pcitag_t adjustment patch for months,
> it can be found attached.
> I should point out - for the naysayers that think having the BDF in bits
> 23-8 is better - on x86 there are dedicated sub-registers for accessing
> bits 15-0, 15-8, and 7-0 of a register word, while there are not for
> bits 23-16 or 31-16, so it turns out that putting the B:DF in bits
> 15-8:7-0 works out pretty well for elegant and compact generated
> assembly code.
> Also, my thought is, that if we ever have to use the 16-bit PCI domain
> number from ACPI, that we can stuff it in bits 31-16 of the pcitag_t,
> rather than have the complexity of introducing a chipset tag for each
Perhaps it is more complicated, but we may end up with more than one
chipset tag per domain, anyway. Each domain will have some resources,
such as physical address regions, that need to be managed independently.
You can bundle all of those resources (and the methods for using them)
into the chipset tag.
dyoung%pobox.com@localhost Urbana, IL (217) 721-9981
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