Re: RouterBoard 133 support

[Arnaud Lacombe <lacombar%gmail.com@localhost>]

David Young wrote:
> > We can think of use case where people would like to have 1 WAN port on 
> > VLAN1, 2 bridged port on VLAN0 seen by the CPU and 3 bridged port 
> > isolated from the CPU and other traffic. In this setup, we would have 
> > the following matrix:
> >           MII0 MII1 MII2 MII3 MII4 MII5 CPU
> >     VLAN0      x    x                   x
> >     VLAN1 x                             x
> >     VLAN2                               x
> >     VLAN3                x
> >     VLAN4                     x
> >     VLAN5                          x
> >
> > In which case the OS would only see 3 interfaces from which it 
> > send/receive traffic, one for each VLAN.
>
> The matrix you have drawn corresponds to this setup:
>
>         ifconfig bridge0 create
>         brconfig bridge0 add admsw1 add admsw2 up
>
>         ifconfig admsw0 up
>
>         ifconfig admsw3 down
>         ifconfig admsw4 down
>         ifconfig admsw5 down
>
> But I think that you may have misplaced your x's in the VLAN3, 4, and
> 5 rows.  I thought that you intended to bridge together ports 3, 4, and 5?
exact, my bad, I was just about to send the correction :)

> > Using vlan(4) would move the processing from the hardware to the kernel 
> > and thus software processing of the data.
>
> Not if vlan(4) delegates to the hardware, as I propose.
cf my last mail of yesterday, the feature provide by the chip does not 
match vlan(4) features.

 - Arnaud