Port-atari archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

SCSI DMA problem on Falcon (Re: gcc4 problem on netbsd-4)

Tuomo wrote:

> > BTW, SCSI DMA on Falcon is disabled in this kernel,
> > i.e. this one also contains the following change:
> > http://mail-index.netbsd.org/source-changes/2008/11/15/msg212774.html
> with-DMA kernel works (but kernel starts to output "St-mem pool exhausted
> messages" on boot; I guess kernel was compiled with ST_POOL_SIZE=22). On
> my Falcon which runs NetBSD, current kernel also worked with 68030 and SCSI
> DMA (Not much tested, but at least I was able to boot up system).
> At least some early Falcon models can have some HW issues with DMA and with
> upgrades some problems might be amplified, so it was decided disable SCSI DMA
> at least for now.
> With 68060 problems started to show. Here's some links to discussion on
> port-atari:
> http://mail-index.netbsd.org/port-atari/2008/10/26/msg000046.html
> http://mail-index.netbsd.org/port-atari/2008/11/14/msg000119.html
> http://mail-index.netbsd.org/port-atari/2008/11/14/msg000120.html

Ah, I see.

Current ncr5380 driver allocates/frees pool memory for
a DMA bounce buffer on per each transfer, but it could cause
a fragmentation problem in the memory pool and it may
prevent allocating contiguous up to 64kbyte buffers
then causes the "pool exhausted" problem.
(BTW in that case DMA seems disabled so the message may be harmless)

I guess this can be solved by allocating a static buffer once at boot.
(though I'm not sure if more than one DMA xfers could happen at once)

The "wrong drive infomation" problem might be caused by
DMA-cache coherency issue. We have to put some cache flush code
around DMA xfer if the hardware doesn't support DMA bus snoop etc.

There is a PCIA() call in ncr5380.c:dma_ready() to invalidate cache
after DMA xfer, but I think it should be done even in !BOUNCING case.
Maybe we also have to writeback cache on 040/060 (since we use PG_CCB)
before DMA is started on write xfers.

But I'm not sure if DMA xfers with cache flush ops is fater enough
than PIO and it's worth to enable it...

Necessary cache ops can be found in sys/arch/m68k/m68k/bus_dma.c and
sys/arch/m68k/include/cacheops*.h, but it could be a bit huge changes.
It's a bit pain to flush whole cache even on very small xfers,
but cache flush ops against small and unaligned buffers often
cause problems or large overheads.
(see comments in bus_dum.c:_bus_dmamap_sync() in PREREAD case)
Izumi Tsutsui

Home | Main Index | Thread Index | Old Index