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Re: i2c working on BeagleBone?



Hi Chris --

I went ahead and checked for you because I'm sure that I didn't pull those numbers out of thin air. The psc/scll/sclh values come from sys/arch/arm/omap/Attic/ti_iic.c r1.14

I2C worked fine on AM335x when I converted it to use device tree, you can see the PMIC and EEPROM drivers attaching here: https://dmesgd.nycbug.org/index.cgi?do=view&id=5174

Let me know if you have any more doubts about the work to adapt this port for FDT.

Take care,
Jared


On Sun, 2 Apr 2023, Chris wrote:

On Sun, Apr 02, 2023 at 11:27:28AM +0200, Radoslaw Kujawa wrote:

I am positive it worked before FDT changes. I remember playing around with various sensors and even testing newly written I2C drivers with the original white BB.

Thanks for the confirmation; now I have a better idea what I'm dealing with.
What version were you working with, so that I can better bisect the code?

The FDT change brought in this:

       /* XXX standard speed only */
       if (sc->sc_type == TI_IIC_OMAP3) {
               psc = (96000000 / 19200000) - 1;
               scll = sclh = (19200000 / (2 * 100000)) - 6;
       } else {
               psc = 3;
               scll = 53;
               sclh = 55;
       }

... which appears to be wrong for OMAP4, wasn't in the code pre-FDT, and raises
more doubts about the rest of the BB post-FDT.

The OMAP3 clock setting makes i2cscan work better with "-r" (see below) but
there are still intermittent and non-deterministic false detections.  I suspect
those are caused by timing/re-entrancy issues.

I don't see how i2cscan ever worked with the TI AM335x chips, as the default
quick-write scheme has a payload size of zero and is silently dropped by
ti_iic.c.

There's more mystery surrounding the second i2c bus (iic1, reserved for cape
EEPROMs).  It's disabled in the dtb, so the FDT code does not enumerate the bus.
Did capes work pre-FDT?

Cheers,

--

-- Chris
  GPG key fingerprint B566 051D D99D 37B6 41F2  7593 22EE 9E38 FBA7 7B34



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