Re: LSE Atomics

[Robert Swindells <rjs%fdy2.co.uk@localhost>]

Martin Husemann <martin%duskware.de@localhost> wrote:
>On Thu, May 07, 2020 at 01:13:21AM +0200, Tobias Nygren wrote:
>> Fetch sysctl machdep.cpu0.cpu_id (see usr.sbin/cpuctl/arch/aarch64.c)
>> Then test the ID_AA64ISAR0_EL1 register bits 23:20 for the value 0b0010.
>
>That doesn't sound safe (what if cpu0 and cpu$N disagree?)

Do we support any big.LITTLE systems ? If so, do the cpus have different
instruction sets or just different speeds.

I was planning to commit a patch to nss that checks for crypto
instructions, currently it just looks at cpu0. I suppose I can change
this to AND together the results from all cpus.